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[130.111.218.23]) by smtp.gmail.com with ESMTPSA id v65-v6sm3608940qkb.91.2018.05.17.09.34.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 May 2018 09:34:58 -0700 (PDT) From: Vince Weaver X-Google-Original-From: Vince Weaver Date: Thu, 17 May 2018 12:34:56 -0400 (EDT) X-X-Sender: vince@macbook-air To: Stefan Wahren cc: Florian Fainelli , Eric Anholt , bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm: bcm2835: Add the PMU to the devicetree. In-Reply-To: <1412187220.62585.1526572780332@email.1und1.de> Message-ID: References: <20180517131727.29263-1-eric@anholt.net> <1412187220.62585.1526572780332@email.1und1.de> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 17 May 2018, Stefan Wahren wrote: > > > Eric Anholt hat am 17. Mai 2018 um 15:17 geschrieben: > > > > > > The a53 and a7 counters seem to match up, so we advertise a7 so that > > arm32 can probe. so how closely did you look at the a53/a7 differences? I see some major differences, especially with the CPU_CYCLES event (0xff vs 0x11). The proper fix here might be to add a cortex-a53 PMU entry to the armv7 code rather than trying to treat it as a cortex-a7. Vince