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[209.132.180.67]) by mx.google.com with ESMTP id r18-v6si4397272pgd.143.2018.05.17.11.07.35; Thu, 17 May 2018 11:07:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=lYu0sLHs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752014AbeEQSH2 (ORCPT + 99 others); Thu, 17 May 2018 14:07:28 -0400 Received: from mail-yb0-f196.google.com ([209.85.213.196]:46305 "EHLO mail-yb0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751233AbeEQSH0 (ORCPT ); Thu, 17 May 2018 14:07:26 -0400 Received: by mail-yb0-f196.google.com with SMTP id f3-v6so1764953ybg.13; Thu, 17 May 2018 11:07:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=58VGKeiftzrbmpZ9jkiavMnXzgqEVlmqWlg6JRF+SbI=; b=lYu0sLHslCOgdRZecHXkeopUUmza6VETVySEbzvl2EgVsBLO1Su5RJq4NDG3Q8rXDA 8MqDYzuZAqBqWl5NCdMJHRveuywpWcEGHm3BiA0vn+vPhygCPK3mbJcYi6EsIUIWPdYT GHkVt6XtWXBN1TZ0ksXFZWzE34B3xJmYeI6swuJ1OaZ4kQ+OvurzwijBeW7vycVRFI03 O9Sg9TEVhaJ8y024mz4OU73f9Z0RSh8tb4bDEFY5zRAig7qJtW2mHYAbqjZGlXT7BuvK jSE+YpKvRRjhXvzXsb9uvh51y3qc4DFWDNbxrrc9WOs2428tDpeFnRkO3LtnptOTfiZ9 CUOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=58VGKeiftzrbmpZ9jkiavMnXzgqEVlmqWlg6JRF+SbI=; b=QPIxXhgCr9OUCb4t8Md5E2rrHgNp6j8zCxZnjYzBEHuFKbm0OP9l34Tc5qy7cMSf+U mu0EDIkbCKi5kxAKBvhbwXg3pbIE4zye8dIZuImQm5AKSQXXCHms5qElyN+ipWoHqGw4 E0SAXCCXaXXraOlyDrFOrpARLlUuqzviny7mil17dRk4O81obA1AeBm3hRJkny+Vtrss IiqRyxDR7YQncRG9oCE0pS10fnyxWtIDPg9RolzTJOoou8etriwr8LvnbQck3ykdGjwL F+nh8rUPHCMetpAipgk2DFH5xqKt2+l4EGbhCQ+cLPGla5wLc296S9NLa4muDSyJI2d+ c4PQ== X-Gm-Message-State: ALKqPwcv4vtu3YcBQWFfWF7okmaefiH6Gt6CvA0Pug7uAhnpADjrASJK +511qPLEkT4SAfADocxBWy4= X-Received: by 2002:a25:3dc5:: with SMTP id k188-v6mr3380935yba.145.1526580445745; Thu, 17 May 2018 11:07:25 -0700 (PDT) Received: from sophia ([72.188.97.40]) by smtp.gmail.com with ESMTPSA id p123-v6sm2308881ywg.31.2018.05.17.11.07.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 May 2018 11:07:25 -0700 (PDT) Date: Thu, 17 May 2018 14:07:07 -0400 From: William Breathitt Gray To: Rob Herring Cc: Jonathan Cameron , Benjamin Gaignard , Fabrice Gasnier , linux-iio@vger.kernel.org, "linux-kernel@vger.kernel.org" , devicetree@vger.kernel.org, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Mark Rutland Subject: Re: [PATCH v6 6/9] dt-bindings: counter: Document stm32 quadrature encoder Message-ID: <20180517180707.GA30194@sophia> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.5 (2018-04-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 17, 2018 at 11:23:22AM -0500, Rob Herring wrote: >On Wed, May 16, 2018 at 12:51 PM, William Breathitt Gray > wrote: >> From: Benjamin Gaignard > >v6? Where's v1-v5? Hi Rob, I apologize, I should have CC you on the rest of the patchset to give you a better idea of the context of this particular patch. Benjamin Gaignard authored this particular patch, so I'll leave it up to him to respond to your inline comments, but I can at least provide a brief history of the revisions of this patchset as a whole. This patchset introduces a "Generic Counter" interface for drivers to support various counter devices (tally counters, rotary encoders, etc.). The v1 revision was submitted on 31 July 2017 (https://lkml.org/lkml/2017/7/31/514) as a wrapper over existing IIO functionality. This implementation design was unsuitable for the needs of Generic Counter API, so the v4 revision submitted on 14 December 2017 reimplemented the Generic Counter API as its own Counter subsystem (https://lkml.org/lkml/2017/12/14/778). The v5 revision was submitted on 9 March 2018 (https://lkml.org/lkml/2018/3/9/728) and introduced the STM32 Timer quadrature encoder driver with Generic Counter interface support. I should have CC you in that revision to comment on the dt-bindings patch, but I overlooked it, so I made sure to CC you on this v6 revision. William Breathitt Gray > >> Add bindings for STM32 Timer quadrature encoder. >> It is a sub-node of STM32 Timer which implement the >> counter part of the hardware. >> >> Cc: Rob Herring >> Cc: Mark Rutland >> Signed-off-by: Benjamin Gaignard >> Signed-off-by: William Breathitt Gray >> --- >> .../bindings/counter/stm32-timer-cnt.txt | 26 +++++++++++++++++++ >> .../devicetree/bindings/mfd/stm32-timers.txt | 7 +++++ >> 2 files changed, 33 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt >> >> diff --git a/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt >> new file mode 100644 >> index 000000000000..377728128bef >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt >> @@ -0,0 +1,26 @@ >> +STMicroelectronics STM32 Timer quadrature encoder >> + >> +STM32 Timer provides quadrature encoder counter mode to detect > >'mode' does not sound like a sub-block of the timers block. > >> +angular position and direction of rotary elements, >> +from IN1 and IN2 input signals. >> + >> +Must be a sub-node of an STM32 Timer device tree node. >> +See ../mfd/stm32-timers.txt for details about the parent node. >> + >> +Required properties: >> +- compatible: Must be "st,stm32-timer-counter". >> +- pinctrl-names: Set to "default". >> +- pinctrl-0: List of phandles pointing to pin configuration nodes, >> + to set IN1/IN2 pins in mode of operation for Low-Power >> + Timer input on external pin. >> + >> +Example: >> + timers@40010000 { >> + compatible = "st,stm32-timers"; >> + ... >> + counter { >> + compatible = "st,stm32-timer-counter"; > >Is there only 1? How is the counter addressed? > >> + pinctrl-names = "default"; >> + pinctrl-0 = <&tim1_in_pins>; >> + }; >> + };