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[209.132.180.67]) by mx.google.com with ESMTP id u74-v6si4338035pgc.186.2018.05.17.14.05.13; Thu, 17 May 2018 14:05:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751995AbeEQVFA (ORCPT + 99 others); Thu, 17 May 2018 17:05:00 -0400 Received: from muru.com ([72.249.23.125]:42908 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751409AbeEQVE6 (ORCPT ); Thu, 17 May 2018 17:04:58 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 5DCC1801E; Thu, 17 May 2018 21:07:02 +0000 (UTC) Date: Thu, 17 May 2018 14:04:50 -0700 From: Tony Lindgren To: Faiz Abbas Cc: linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, bcousson@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, paul@pwsan.com, lokeshvutla@ti.com, linux@armlinux.org.uk Subject: Re: [PATCH 1/3] ARM: dra762: hwmod: Add MCAN support Message-ID: <20180517210450.GP98604@atomide.com> References: <1523181542-3770-1-git-send-email-faiz_abbas@ti.com> <1523181542-3770-2-git-send-email-faiz_abbas@ti.com> <20180501152615.GB98604@atomide.com> <20180515171459.GP98604@atomide.com> <20180515171808.GR98604@atomide.com> <20180515172324.GS98604@atomide.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Faiz Abbas [180517 08:14]: > On Tuesday 15 May 2018 10:53 PM, Tony Lindgren wrote: > > And I'm guessing the top level module with sysconfig related > > registers is named "adc" :) > > > > Yes. The MCAN clocks are controlled by the ADC_CLKCTRL register. > Please see TRM: > http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=spruie9&fileType=pdf > page: 1530 Thanks that helps :) Looks like we have: MCANSS_PID rev 0 MCANSS_CTRL sysconfig 0x4 MCANSS_STAT sysstatus 0x8 With current Linux next, this should work with just ti-sysc if we added yet another sysconfig layout.. See Documentation/devicetree/bindings/bus/ti-sysc.txt Looks like this is not quite "ti,sysc-omap4" as there are no ti,sysc-midle or ti,sysc-sidle, and sysstatus reset bit is inverted.. Anyways, I think the dts part should be similar to this with the new sysconfig added (untested): target-module@42c00000 { compatible ="ti,sysc-yet-to-be-determined"; ti,hwmods = "mcan"; reg = <0x42c00000 4>, <0x42c00004 4>, <0x42c00008 4>; reg-names = "rev", "sysc", "syss"; clocks = <&wkupaon_clkctrl CM_WKUPAON_ADC_CLKCTRL>; clock-names = "fck"; ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | SYSC_DRA7_ENAWAKEUP)>; ti,syss-mask = <1>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x42c00000 0x2000>; mcan@0 { compatible = "bosch,m_can"; reg = <0x1a00 0x4000>, <0 0x18fc>; reg-names = "m_can", "message_ram"; interrupt-parent = <&gic>; interrupts = , ; interrupt-names = "int0", "int1"; clocks = <&mcan_clk>, <&l3_iclk_div>; clock-names = "cclk", "hclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>; }; }; You'd have to add a new struct sysc_regbits to ti-sysc.c similar to sysc_regbits_omap4 for the .srst_shift = 0. Not sure if the same register layout is used for other modules, but might be worth checking the TRM. Also the clock node is missing for wkupaon_clkctrl from include/dt-bindings/clock/dra7.h. If the "message_ram" can operate independent of the driver, it could be a separate child node under the target-module. In the hwmod you still need the struct omap_hwmod for now, but clocks should no longer be needed there. Regards, Tony