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[209.132.180.67]) by mx.google.com with ESMTP id e5-v6si5677933pgs.317.2018.05.18.02.49.55; Fri, 18 May 2018 02:50:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=PIEIsEnd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752847AbeERJrx (ORCPT + 99 others); Fri, 18 May 2018 05:47:53 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:45749 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752208AbeERJru (ORCPT ); Fri, 18 May 2018 05:47:50 -0400 Received: by mail-pf0-f195.google.com with SMTP id c10-v6so3497696pfi.12 for ; Fri, 18 May 2018 02:47:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A5/aqEXOiUc5X1oMe585eNqcQtPqceVw+bFSUrhT5UM=; b=PIEIsEnd5BgruqM1+ImRLujkOpWquogn7xG4vo3pIjC7d6lEtzltp4H5LRuILuLgKO 6EW3R2yL/Lv3e6Wv4hV2dy2YwToi/At/XU359n5DOJSulOwIE7uSnCFZiJT9zR4CYEUR 5E84KxfxEW3vdq92yWb9pE2feMmlWZ3kLZ79I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A5/aqEXOiUc5X1oMe585eNqcQtPqceVw+bFSUrhT5UM=; b=YdCvLu0mOiuecMYO20DYCqCnOPzp+mlPK0p9BD/cNcTp2sMQroBItl/6D69fR/Ofb8 BO0jB5e0/nS4SgSKBLGUpg326XxV0AFQD6bf/ewgdtM5tKGgei5lB7wt6Iq0pp9FF6jN zEPggOJfAQFVmCPv95vEMRqTrsdcZf28vVPQWGQL63gUYlvAVW//heAIjY4RAfvKcPU/ FKOnWY3kzX8GuO30RY9dG1gPmj29jQQ8LfI8qrd+NcoEFsmWNutX9YxBD26KuGeA6YWK iDwoQLPnVGGS9kZsm59oeurLiFpMnDKDefsd0xfw8Mdw3e/M8twX/7G2nObq/mCcaGRs o5BQ== X-Gm-Message-State: ALKqPwcGc4Cwqvu7UBweaUcDUC0LHWrcjOxs/kzloiFuK7gJzWrx0ngg RyZ8LvYKU3Lv8hW7OOwhCR8tmw== X-Received: by 2002:a63:5f01:: with SMTP id t1-v6mr936113pgb.94.1526636869715; Fri, 18 May 2018 02:47:49 -0700 (PDT) Received: from localhost.localdomain ([183.82.227.74]) by smtp.gmail.com with ESMTPSA id j11-v6sm12694097pff.64.2018.05.18.02.47.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 18 May 2018 02:47:49 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jernej Skrabec , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , David Airlie , dri-devel@lists.freedesktop.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Michael Trimarchi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Jagan Teki Subject: [PATCH v2 16/26] dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO[0-1] macros Date: Fri, 18 May 2018 15:15:26 +0530 Message-Id: <20180518094536.17201-17-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com> References: <20180518094536.17201-1-jagan@amarulasolutions.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Allwinner A64 has two clock parents PLL_VIDEO0 and PLL_VIDEO1. Include these macros on dt-bindings so-that the same can be used while defining CCU clock phadles. Signed-off-by: Jagan Teki --- Changes for v2: - new patch include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index d66432c6e675..d1d7d5b7d06a 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -43,7 +43,9 @@ #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ #define _DT_BINDINGS_CLK_SUN50I_A64_H_ +#define CLK_PLL_VIDEO0 7 #define CLK_PLL_PERIPH0 11 +#define CLK_PLL_VIDEO1 15 #define CLK_BUS_MIPI_DSI 28 #define CLK_BUS_CE 29 -- 2.14.3