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[209.132.180.67]) by mx.google.com with ESMTP id x12-v6si5655339pgv.556.2018.05.18.02.51.04; Fri, 18 May 2018 02:51:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752744AbeERJtO (ORCPT + 99 others); Fri, 18 May 2018 05:49:14 -0400 Received: from esa6.microchip.iphmx.com ([216.71.154.253]:27533 "EHLO esa6.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752657AbeERJsz (ORCPT ); Fri, 18 May 2018 05:48:55 -0400 X-IronPort-AV: E=Sophos;i="5.49,414,1520924400"; d="scan'208";a="11672337" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 18 May 2018 02:48:55 -0700 Received: from [10.145.4.57] (10.10.76.4) by chn-sv-exch05.mchp-main.com (10.10.76.106) with Microsoft SMTP Server id 14.3.352.0; Fri, 18 May 2018 02:48:54 -0700 Subject: Re: [PATCH] mtd: spi-nor: add support for Microchip 25LC256 To: Marek Vasut , Boris Brezillon CC: , , , , , , References: <20180504155404.5285-1-radu.pirea@microchip.com> <20180504204013.254d90cf@bbrezillon> <1db092c8-95fb-5747-f7b9-f6a215b1aa5b@gmail.com> <30ab9516-abc9-d2d5-79ea-266c682c5fa9@gmail.com> From: Radu Pirea Message-ID: <1993151b-4434-c671-8498-b6488288f5f6@microchip.com> Date: Fri, 18 May 2018 12:50:11 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <30ab9516-abc9-d2d5-79ea-266c682c5fa9@gmail.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/16/2018 04:47 PM, Marek Vasut wrote: > On 05/16/2018 12:05 PM, Radu Pirea wrote: >> On Wed, 2018-05-16 at 00:17 +0200, Marek Vasut wrote: >>> On 05/15/2018 06:22 PM, Radu Pirea wrote: >>>> On Fri, 2018-05-04 at 20:40 +0200, Boris Brezillon wrote: >>>>> On Fri, 4 May 2018 18:54:04 +0300 >>>>> Radu Pirea wrote: >>>>> >>>>>> Added geometry description for Microchip 25LC256 memory. >>>>> >>>>> Same as for the dataflash stuff you posted a few weeks ago: I >>>>> don't >>>>> think this device belongs in the SPI NOR framework. >>>> >>>> Hi Boris, >>>> >>>> 25lc256 memory is similar with mr25h256, the only difference is the >>>> page size(64 vs 256). Because mr25h256 is already in SPI NOR >>>> framework >>>> I added here 25lc256. >>> >>> I think I must be reading the wrong datasheet, but can you show me >>> how >>> does it support things like READID opcode ? >>> >> Hi Marek, >> >> I read the datasheet for 25lc256 and for mr25h256 and none of them >> supports READID. Is this required for a chip to be included in spi-nor >> framework? I just followed the mr25h256 as an example. > > So I thought until you pointed out the MR25 devices. > > Does the 25LC device need erase or not ? I think the MR25s didn't, but I > might be wrong. You are right. MR25s does not need erase and the same thing is true for 25LC. > > Maybe the framework could support the 25LC afterall. > Yes, this was my impression too. Thanks.