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[209.132.180.67]) by mx.google.com with ESMTP id d8-v6si5390575pgu.671.2018.05.18.08.35.37; Fri, 18 May 2018 08:35:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751488AbeERPfd convert rfc822-to-8bit (ORCPT + 99 others); Fri, 18 May 2018 11:35:33 -0400 Received: from mailout11.siol.net ([213.250.19.138]:58079 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750763AbeERPfa (ORCPT ); Fri, 18 May 2018 11:35:30 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 1C0C5520182; Fri, 18 May 2018 17:35:26 +0200 (CEST) X-Virus-Scanned: amavisd-new at psrvmta10.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta10.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id erNJB8rAPtH1; Fri, 18 May 2018 17:35:25 +0200 (CEST) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 8CB9C520130; Fri, 18 May 2018 17:35:25 +0200 (CEST) Received: from jernej-laptop.localnet (unknown [194.152.15.144]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPA id 25D32520182; Fri, 18 May 2018 17:35:24 +0200 (CEST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Maxime Ripard Cc: Jagan Teki , Chen-Yu Tsai , Icenowy Zheng , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , David Airlie , dri-devel@lists.freedesktop.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Michael Trimarchi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH v2 12/26] drm/sun4i: Add support for multiple DW HDMI PHY clock parents Date: Fri, 18 May 2018 17:34:48 +0200 Message-ID: <3855913.NIurOIk8c1@jernej-laptop> In-Reply-To: <20180518152651.lfymc3kj7npj5tww@flea> References: <20180518094536.17201-1-jagan@amarulasolutions.com> <4909574.Q3IFWM0xt6@jernej-laptop> <20180518152651.lfymc3kj7npj5tww@flea> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a): > On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote: > > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to > > > lookup pll-2 either. > > > > It is highly unlikely this will be higher than 2, at least for this HDMI > > PHY, since it has only 1 bit reserved for parent selection. But since I > > have to fix it, I'll add ">= 2" > > If we're only going to have two parents at most, ever, why don't we > had just a single other boolean. This would be less intrusive, and we > wouldn't have to check for those corner cases. That works for me too. And since it's only the code, it can always be reworked if there is the need. Best regards, Jernej > > > BTW, I'll resend fixed version of this patch for my R40 HDMI series, since > > there is nothing to hold it back, unlike for this. > > Awesome, thanks! > Maxime > > -- > Maxime Ripard, Bootlin (formerly Free Electrons) > Embedded Linux and Kernel engineering > https://bootlin.com