Received: by 2002:ac0:a594:0:0:0:0:0 with SMTP id m20-v6csp4731674imm; Fri, 18 May 2018 09:43:09 -0700 (PDT) X-Google-Smtp-Source: AB8JxZozCGTqR794O/VHPMctnKrBTBKOtp8GRjhdqiZnr7FgN0nboErUf4I/vnFI9afE3KVbmHUU X-Received: by 2002:a63:8ac4:: with SMTP id y187-v6mr8065842pgd.64.1526661789526; Fri, 18 May 2018 09:43:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526661789; cv=none; d=google.com; s=arc-20160816; b=S5Xq0KOl0nLeQqhA1LS5wlSP4Qvkims15t/4HB3evaGLfCFRS6ypxq8nPK33dLLrS2 AeiTS/TkW+Rto0EsEXbZk6NDWsyvRY6plhFGrv8dKW9NRm4g69VHEQMLuTJkESxyH3Jj +o+2FpODfnjyHWKIf3iTzb91o+w5o+8nqiCTaFIQqG5KtQ6r0NluW7f1dIDsnsJEngYO XXEz0WEcIAuTwZsDzfPx9P+wYYKxfFyXqQKl0Y9LhLIvkcEssxP9T5MHbuNZ/NeZSeGJ urDqg+kjoROautNo97AFcqnPaz3hA8P5YxUE7mGgxMP5qQqszZ4yBCOcxkMmDsOmiz4u xctg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:organization:from:references:cc:to:subject :arc-authentication-results; bh=VMBxUwRmKGpQ3z1Jf/9Ge5ehXHtASafYx2zzmSber4g=; b=wqNkP19dLJsnaMg8WOgUxm7gf6AuaWF2UVvuXNVBgB4QUZ/QoJK19xJE8CFG0w/Cxi H4ApHSg+XnrLeA2AMfT7CmM1DeDOPDwcH+vEJkC7Q/iTJutd+I4B/CtYGRB5uZaABZYT AtqdVAmiAHPlaK5CYQG4H4LDcn1mB3USJ8ULODYgFwINCOsFY5sW2wOGyK70J9x0JNs9 wWlEPlCPg3BHwxXoN1tPkqX9x6eiiuUDUenffcXrxkbsHNH4xHPjF4G8XX0GzPzD8ce8 TBtVZcfeygEoXy8oSQwEz5KycIbS7D7LpqHV0eC0E2IRXORw5beDWlElllrJI3h98ywD Uq0A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q12-v6si7373839plr.358.2018.05.18.09.42.55; Fri, 18 May 2018 09:43:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752528AbeERQlS (ORCPT + 99 others); Fri, 18 May 2018 12:41:18 -0400 Received: from foss.arm.com ([217.140.101.70]:56242 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752513AbeERQlN (ORCPT ); Fri, 18 May 2018 12:41:13 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 43CA91529; Fri, 18 May 2018 09:41:13 -0700 (PDT) Received: from [10.1.206.75] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 608FB3F25D; Fri, 18 May 2018 09:41:11 -0700 (PDT) Subject: Re: [PATCH v3 0/5] To: Vince Weaver Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Will Deacon , Mark Rutland , Russell King , Vladimir Murzin , Peter Zijlstra , Stefan Wahren , Eric Anholt , Florian Fainelli References: <20180518143913.26306-1-marc.zyngier@arm.com> From: Marc Zyngier Organization: ARM Ltd Message-ID: <278cb8b1-d567-2067-2dde-980596821c9c@arm.com> Date: Fri, 18 May 2018 17:41:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [/me beats himself for not writing a subject line...] On 18/05/18 17:29, Vince Weaver wrote: > On Fri, 18 May 2018, Marc Zyngier wrote: > >> There is also the case of people natively running 32bit kernels on >> 64bit HW and trying to upstream unspeakable hacks, hoping that the >> stars will align and that they'll win the lottery (see [1]). > > I've tested these patches on a Raspberry Pi 3B running a 32-bit upstream > (4.17-rc5-git) kernel and they work. > > [ 0.472906] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available > > I only needed to add this to the devicetree > > arm-pmu { > compatible = "arm,cortex-a53-pmu"; > interrupt-parent = <&local_intc>; > interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; > }; That's definitely the sensible thing to have on such hardware. Why isn't it in the upstream DT already, irrespective of the state of the kernel support? > Tested-by: Vince Weaver Thanks a lot for testing. M. -- Jazz is not dead. It just smells funny...