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[209.132.180.67]) by mx.google.com with ESMTP id v1-v6si7213701pgr.30.2018.05.19.03.12.21; Sat, 19 May 2018 03:12:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V+5LP+EV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752304AbeESKMF (ORCPT + 99 others); Sat, 19 May 2018 06:12:05 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:45585 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752206AbeESKMC (ORCPT ); Sat, 19 May 2018 06:12:02 -0400 Received: by mail-pl0-f66.google.com with SMTP id bi12-v6so6003833plb.12 for ; Sat, 19 May 2018 03:12:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=EZK8X4NFCed+btfj3V3EOjpCPthybnwWcqAMPvj+z/k=; b=V+5LP+EVzK8gnm1EyT4JUKu6DqEtmSTla49tU0XvWJCySxfyEv7R21by+bZCqM5l6A jl523qUXTxbKpZXmvju3UQwDRcuI+Sygq+EuRuJklVuLyy65WgzTCLJrzbT5qtIkC9Kv mqSQQEdvVYbUSSG+uv4bvr2PFtPuj67ScMok8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=EZK8X4NFCed+btfj3V3EOjpCPthybnwWcqAMPvj+z/k=; b=DQkIBSlrz/BaMNwKYQjiU7IzbQCEzFTnPcEmdjG20ecTXJno3uGkTrrh8BkT7eDh9b bNh2FJ6cgcrBb2IXhUaBU5CK1wA7Sx6h+gYMN0YegGoiY1XL4Bl3Va9yU2/ZI8dLhXKm Wiyz8ikxMX8OGIzl7gdN74AGtqkmWaRhBbUlkYtjh0bKhhCh7sBPZRvf9WDwCe0xkUKW gmV7Hc9jUckDRTB9U3mIY6sUoVlCdan02fQv4hflxTK9K2irFormMjbKoo/sQfO2WtOx dUz7tEVVdc9K4Wt7ooct2DJA6Vt3dGxF8O7h19+GD1eKF3GDTGRELaCEqDXLfBSuqQca orQA== X-Gm-Message-State: ALKqPwfBJ5JEXlEchAlbK/ZYqxy/8S0R496qAYUbCAcHHCO1b3RdynDM qbQcis2hlSVnHponFANgBWSO X-Received: by 2002:a17:902:294a:: with SMTP id g68-v6mr13123525plb.110.1526724721732; Sat, 19 May 2018 03:12:01 -0700 (PDT) Received: from linaro.org ([2405:204:7088:28e3:f44b:e180:869f:1cf]) by smtp.gmail.com with ESMTPSA id h130-v6sm28563852pfc.98.2018.05.19.03.11.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 19 May 2018 03:12:00 -0700 (PDT) Date: Sat, 19 May 2018 15:41:49 +0530 From: Manivannan Sadhasivam To: Christian Lamparter Cc: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com Subject: Re: [PATCH 4/5] pinctrl: actions: Add gpio support for Actions S900 SoC Message-ID: <20180519101149.7bq6vjiibyrsedv3@linaro.org> References: <20180518023056.7869-1-manivannan.sadhasivam@linaro.org> <20180518023056.7869-5-manivannan.sadhasivam@linaro.org> <12834501.5lBvNSZm06@debian64> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <12834501.5lBvNSZm06@debian64> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Christian, On Sat, May 19, 2018 at 11:18:53AM +0200, Christian Lamparter wrote: > On Friday, May 18, 2018 4:30:55 AM CEST Manivannan Sadhasivam wrote: > > Add gpio support to pinctrl driver for Actions Semi S900 SoC. > > > > Signed-off-by: Manivannan Sadhasivam > > --- > > [...] > > +static int owl_gpio_init(struct owl_pinctrl *pctrl) > > +{ > > + struct gpio_chip *chip; > > + int ret; > > + > > + chip = &pctrl->chip; > > + chip->base = -1; > > + chip->ngpio = pctrl->soc->ngpios; > > + chip->label = dev_name(pctrl->dev); > > + chip->parent = pctrl->dev; > > + chip->owner = THIS_MODULE; > > + chip->of_node = pctrl->dev->of_node; > > + > > + ret = gpiochip_add_data(&pctrl->chip, pctrl); > > + if (ret) { > > + dev_err(pctrl->dev, "failed to register gpiochip\n"); > > + return ret; > > + } > > + > > + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), > > + 0, 0, chip->ngpio); > > + if (ret) { > > + dev_err(pctrl->dev, "failed to add pin range\n"); > > + gpiochip_remove(&pctrl->chip); > > + return ret; > > + } > > + > gpiochip_add_pin_range()? That's not going to work with gpio-hogs. > Hmmm. Just looked into the gpio-hog mechanism and the patch you have implemented for MSM driver. I agree with you on replacing gpiochip_add_pin_range() with gpio-ranges property. But I'm curious whether we should document it somewhere or not (probably in [1]). Anyway I will send the v2 incorporating your suggestion. Thanks, Mani [1] Documentation/devicetree/bindings/gpio/gpio.txt > But, you can easily test this. Just add a gpio-hog [0] > ( Section 2. gpio-controller nodes) into the Devicetree's > pinctrl node. > > something like: (No idea if GPIO1 is already used, but any free > gpio will do) > | [...] > | pinctrl@e01b0000 { > | compatible = "actions,s900-pinctrl"; > | reg = <0x0 0xe01b0000 0x0 0x1000>; > | clocks = <&cmu CLK_GPIO>; > | gpio-controller; > | #gpio-cells = <2>; > | > | line_b { > | gpio-hog; > | gpios = <1 GPIO_ACTIVE_HIGH>; > | output-low; > | line-name = "foo-bar-gpio"; > | }; > | }; > > The pinctrl probe will fail. You can fix this by > replacing the gpiochip_add_pin_range() and use > the gpio-ranges [0] property to define the range. > > [0] > > >