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[209.132.180.67]) by mx.google.com with ESMTP id j8-v6si10388138plk.0.2018.05.19.18.58.26; Sat, 19 May 2018 18:58:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=WAFUWFId; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752552AbeETB6O (ORCPT + 99 others); Sat, 19 May 2018 21:58:14 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:38213 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752531AbeETB6L (ORCPT ); Sat, 19 May 2018 21:58:11 -0400 Received: by mail-wr0-f193.google.com with SMTP id 94-v6so12662817wrf.5; Sat, 19 May 2018 18:58:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=MTNpzPiMFTbEmvDXJQfo//BmLjLyTqno4m4d+JNcp1g=; b=WAFUWFIdI77XBgsTZ1H66l/NhjeHHTWASOQcfV5GDL1LftbqdXxb9DSaWXl5QnPplB Sydvxu9ixkyJcbvZ5rFOf44V+z7PBmQ3V8oVZNHMznOAEnP9H3GxXYnvnQLJlVFJlc6l o0kjYTCtLYb8wN/Oz+tsTcVypbIm2Ke9ntKO6EA5P0SgrXLCxvnBjY81UaRBoT6srsVt 4DRBXc4K/0vNeSjLV5tylCs+9VaZlX42wLrxsSu2vWbSQPs58cH8OOVI7ytEKxvjRDaV BtUOoW2AOwTXKoVtHmhY2eW2TC9TdwJXHmQ2Ry1x+6H238DH7dJcE3zr7YR8mQy1Wi6X zHMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=MTNpzPiMFTbEmvDXJQfo//BmLjLyTqno4m4d+JNcp1g=; b=d/RqtOgJRLb1Ev2O3wDvSUWDsTJSOn6hp/MmcXmj1m4ibO2HM+d7YUwS0ACC4P/ywH H6Oivk6IZZL9/Ec8ZXkMlo0B9V4B+QRttsZRcIx9KGsP4HqUZaPcOdiypN0nQTag1P/p Ikop/6RRo4LKjNyrFxlICQeXwEwbkBCQRAan9B4k3potjUDloPhnuAtY7UYPoKhaOGOf n5UUkbJ+J9B2rvczX0pCRBUpPMOLS4NLcs3qH6sbYFGxh9Tm0oP02zjxCx/wnCvvJ2uF qZ3VwwdDhju48tQ1IQHuYTHYSB+exw82dxzGjcgx+Zv5BpCjPF69QTLuKPP0Etn2oRFE QyUg== X-Gm-Message-State: ALKqPwegnY3DP+oJLEB7EcYspCY5jxbl655GmjccY35xPm6xyt6K69pg r4WNLKTxthk4WJKlbyz972wcqpzcV0FLVJl4KYw= X-Received: by 2002:adf:cd08:: with SMTP id w8-v6mr12493971wrm.187.1526781490231; Sat, 19 May 2018 18:58:10 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.155.136 with HTTP; Sat, 19 May 2018 18:57:49 -0700 (PDT) In-Reply-To: <20180519183127.2718-11-jernej.skrabec@siol.net> References: <20180519183127.2718-1-jernej.skrabec@siol.net> <20180519183127.2718-11-jernej.skrabec@siol.net> From: Julian Calaby Date: Sun, 20 May 2018 11:57:49 +1000 Message-ID: Subject: Re: [linux-sunxi] [PATCH 10/15] drm/sun4i: Add support for R40 TV TCONs To: jernej.skrabec@siol.net Cc: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland , dri-devel , devicetree , "Mailing List, Arm" , "linux-kernel@vger.kernel.org" , "open list:COMMON CLK FRAMEWORK" , linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jernej, On Sun, May 20, 2018 at 4:31 AM, Jernej Skrabec wrote: > R40 display pipeline has a lot of possible configurations. HDMI can be > connected to 2 different TCONs (out of 4) and mixers can be connected to > any TCON. All this must be configured in TCON TOP. > > Along with definition of TCON capabilities also add mux callback, which > can configure this complex pipeline. > > For now, only TCON TV is supported. > > Signed-off-by: Jernej Skrabec > --- > drivers/gpu/drm/sun4i/sun4i_tcon.c | 39 ++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c > index e0c562ce1c22..81b9551e4f78 100644 > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > @@ -1274,6 +1274,31 @@ static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, > return 0; > } > > +static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon, > + const struct drm_encoder *encoder, > + int index) > +{ > + if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) > + sun8i_tcon_top_set_hdmi_src(tcon->tcon_top, index); > + > + sun8i_tcon_top_de_config(tcon->tcon_top, tcon->id, > + tcon_type_tv, index); > + > + return 0; > +} > + > +static int sun8i_r40_tcon_tv_set_mux_0(struct sun4i_tcon *tcon, > + const struct drm_encoder *encoder) > +{ > + return sun8i_r40_tcon_tv_set_mux(tcon, encoder, 0); > +} > + > +static int sun8i_r40_tcon_tv_set_mux_1(struct sun4i_tcon *tcon, > + const struct drm_encoder *encoder) > +{ > + return sun8i_r40_tcon_tv_set_mux(tcon, encoder, 1); > +} Are TCON-TOPs going to be a common thing in new SoCs from Allwinner? If so, maybe we should add an index to the TCON quirks and have a common TCON-TOP set_mux function. Thanks, -- Julian Calaby Email: julian.calaby@gmail.com Profile: http://www.google.com/profiles/julian.calaby/