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[209.132.180.67]) by mx.google.com with ESMTP id y8-v6si11164352pli.242.2018.05.19.19.10.24; Sat, 19 May 2018 19:10:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=d/nv2pJj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752532AbeETCKP (ORCPT + 99 others); Sat, 19 May 2018 22:10:15 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:38349 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752188AbeETCKN (ORCPT ); Sat, 19 May 2018 22:10:13 -0400 Received: by mail-wm0-f65.google.com with SMTP id m129-v6so21053006wmb.3; Sat, 19 May 2018 19:10:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=z3msfdvXACs3/0FXhZ4+SvpqhiF9S9oIIqgVGhbO6Xk=; b=d/nv2pJj3E180TwQUx1bJ2Dbj1NRuErMBI70oM8R/IS1qbIX0x/qkTqYo+MstJnwwe shpTIpUQlRk7sjHhVwqw1EFhP2XJyX/7NqfjM0qsA5+NRWd0uJua4nxeHS8C5JeiqRlz l5mS/A5H9hHwWxM2A2u3ozA7/BMQMvn7bluaOUWkIdrfNUbPsb6MhTWPvtcbSVUraTH9 kFIDGYPwK/jc7fsSm/MhWPiduj4oRG0Cs+yC4/U39VwjGCitc9gCZlZobFCuZvIkG8M9 kMuULda2bxKbZKoeitqCWpv/1+9THUMTb9QhM7eTDKMLDraqBxdZZxpeBFEHCGHKLtEk vD0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=z3msfdvXACs3/0FXhZ4+SvpqhiF9S9oIIqgVGhbO6Xk=; b=M3IpS6S2spuXLP8z907E8dOV60l5vW+81WSFkWKTuStvvtff+QzCITZzRHCJX1yEmz IDM5WKJPdjk29wOQBsmCMUd5y9gnacpa99HLQTSdXgyNii12ISsb7hwklX7VnxgAKtnq tFvl2cww3n9yML0MJoJi4A747YdvO+KTP5KWePrX1MBoIgPhgY97TlVYLw8myBQjYj7r lRZJLUzeGNmdd6YzWjpg6u0AgxX4dofpcJVFa3x6t6Vnlbofo3wtgkgEbyLuQDZyerG8 x2tvTnvUBTgs2ZlhOpG0QGtAGTY2ZK/A8iJ2l6EOUEd2bnVwtyN2CkGxOToUOyrhTSeT OxVQ== X-Gm-Message-State: ALKqPwdSAkV87oRFplyEvdvN6TcxG8SYCTxzfBuG8qLgIYTHdJCdwLmG 9sFOmVfujoVLrNhD/pH1n84ZPh7PctVzdRazQCk= X-Received: by 2002:a1c:80e:: with SMTP id 14-v6mr8161543wmi.9.1526782212375; Sat, 19 May 2018 19:10:12 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.155.136 with HTTP; Sat, 19 May 2018 19:09:52 -0700 (PDT) In-Reply-To: References: <20180519183127.2718-1-jernej.skrabec@siol.net> <20180519183127.2718-11-jernej.skrabec@siol.net> From: Julian Calaby Date: Sun, 20 May 2018 12:09:52 +1000 Message-ID: Subject: Re: [linux-sunxi] [PATCH 10/15] drm/sun4i: Add support for R40 TV TCONs To: jernej.skrabec@siol.net Cc: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland , dri-devel , devicetree , "Mailing List, Arm" , "linux-kernel@vger.kernel.org" , "open list:COMMON CLK FRAMEWORK" , linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jernej, On Sun, May 20, 2018 at 11:57 AM, Julian Calaby wrote: > Hi Jernej, > > On Sun, May 20, 2018 at 4:31 AM, Jernej Skrabec wrote: >> R40 display pipeline has a lot of possible configurations. HDMI can be >> connected to 2 different TCONs (out of 4) and mixers can be connected to >> any TCON. All this must be configured in TCON TOP. >> >> Along with definition of TCON capabilities also add mux callback, which >> can configure this complex pipeline. >> >> For now, only TCON TV is supported. >> >> Signed-off-by: Jernej Skrabec >> --- >> drivers/gpu/drm/sun4i/sun4i_tcon.c | 39 ++++++++++++++++++++++++++++++ >> 1 file changed, 39 insertions(+) >> >> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c >> index e0c562ce1c22..81b9551e4f78 100644 >> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c >> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c >> @@ -1274,6 +1274,31 @@ static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, >> return 0; >> } >> >> +static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon, >> + const struct drm_encoder *encoder, >> + int index) >> +{ >> + if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) >> + sun8i_tcon_top_set_hdmi_src(tcon->tcon_top, index); >> + >> + sun8i_tcon_top_de_config(tcon->tcon_top, tcon->id, >> + tcon_type_tv, index); >> + >> + return 0; >> +} >> + >> +static int sun8i_r40_tcon_tv_set_mux_0(struct sun4i_tcon *tcon, >> + const struct drm_encoder *encoder) >> +{ >> + return sun8i_r40_tcon_tv_set_mux(tcon, encoder, 0); >> +} >> + >> +static int sun8i_r40_tcon_tv_set_mux_1(struct sun4i_tcon *tcon, >> + const struct drm_encoder *encoder) >> +{ >> + return sun8i_r40_tcon_tv_set_mux(tcon, encoder, 1); >> +} > > Are TCON-TOPs going to be a common thing in new SoCs from Allwinner? > If so, maybe we should add an index to the TCON quirks and have a > common TCON-TOP set_mux function. Actually, that only moves it up a level. Should it be a devicetree property? Thanks, -- Julian Calaby Email: julian.calaby@gmail.com Profile: http://www.google.com/profiles/julian.calaby/