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[209.132.180.67]) by mx.google.com with ESMTP id 73-v6si12224174pfh.315.2018.05.20.08.48.55; Sun, 20 May 2018 08:49:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=u8F1pjeC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752541AbeETPrc (ORCPT + 99 others); Sun, 20 May 2018 11:47:32 -0400 Received: from mail.kernel.org ([198.145.29.99]:51268 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751547AbeETPr3 (ORCPT ); Sun, 20 May 2018 11:47:29 -0400 Received: from archlinux (cpc91196-cmbg18-2-0-cust659.5-4.cable.virginm.net [81.96.234.148]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0710F2075C; Sun, 20 May 2018 15:47:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1526831249; bh=dx5Gpqzf3fV410OpTkovIyVBJx4Lx/Zr4GSsx1kOwf4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=u8F1pjeCgAgdFOFbI+ZjOXq+ze26UQfHAzVHQKzIbVGYz4UTsClWdwGNSqrpSey1d V9iOz6tmnP9woPh1Hobggeupnvl5NbA5kYcTW5Hl3SbiiOEzT4leC8KfJH54MW06Pv m3iBFCiLM43xE4EDpqVIV8bSAK7AH2jB0cgkVobk= Date: Sun, 20 May 2018 16:47:23 +0100 From: Jonathan Cameron To: Rob Herring Cc: Benjamin Gaignard , William Breathitt Gray , Mark Rutland , devicetree@vger.kernel.org, Benjamin Gaignard , linux-iio@vger.kernel.org, "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Fabrice Gasnier Subject: Re: [PATCH v6 6/9] dt-bindings: counter: Document stm32 quadrature encoder Message-ID: <20180520164723.20218dfc@archlinux> In-Reply-To: <20180518162815.GA24966@rob-hp-laptop> References: <20180518162815.GA24966@rob-hp-laptop> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 18 May 2018 11:28:15 -0500 Rob Herring wrote: > On Thu, May 17, 2018 at 08:59:40PM +0200, Benjamin Gaignard wrote: > > 2018-05-17 18:23 GMT+02:00 Rob Herring : > > > On Wed, May 16, 2018 at 12:51 PM, William Breathitt Gray > > > wrote: > > >> From: Benjamin Gaignard > > > > > > v6? Where's v1-v5? > > > > > >> Add bindings for STM32 Timer quadrature encoder. > > >> It is a sub-node of STM32 Timer which implement the > > >> counter part of the hardware. > > >> > > >> Cc: Rob Herring > > >> Cc: Mark Rutland > > >> Signed-off-by: Benjamin Gaignard > > >> Signed-off-by: William Breathitt Gray > > >> --- > > >> .../bindings/counter/stm32-timer-cnt.txt | 26 +++++++++++++++++++ > > >> .../devicetree/bindings/mfd/stm32-timers.txt | 7 +++++ > > >> 2 files changed, 33 insertions(+) > > >> create mode 100644 Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt > > >> > > >> diff --git a/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt > > >> new file mode 100644 > > >> index 000000000000..377728128bef > > >> --- /dev/null > > >> +++ b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt > > >> @@ -0,0 +1,26 @@ > > >> +STMicroelectronics STM32 Timer quadrature encoder > > >> + > > >> +STM32 Timer provides quadrature encoder counter mode to detect > > > > > > 'mode' does not sound like a sub-block of the timers block. > > > > quadrature encoding is one of the counting modes of this hardware > > block which is enable to count on other signals/triggers > > You don't need a child node and compatible to set a mode. A pile of extra hardware becomes relevant and you only want to be in this state if you have appropriate external device wired up. In this case there is admittedly not a lot here but some devices will look a bit more like a touchscreen controller. They are often build on top of an ADC module, but have a load of touch screen only signals and electrical elements that warrant being represented as a separate node in the DT. > > > >> +angular position and direction of rotary elements, > > >> +from IN1 and IN2 input signals. > > >> + > > >> +Must be a sub-node of an STM32 Timer device tree node. > > >> +See ../mfd/stm32-timers.txt for details about the parent node. > > >> + > > >> +Required properties: > > >> +- compatible: Must be "st,stm32-timer-counter". > > >> +- pinctrl-names: Set to "default". > > >> +- pinctrl-0: List of phandles pointing to pin configuration nodes, > > >> + to set IN1/IN2 pins in mode of operation for Low-Power > > >> + Timer input on external pin. > > >> + > > >> +Example: > > >> + timers@40010000 { > > >> + compatible = "st,stm32-timers"; > > >> + ... > > >> + counter { > > >> + compatible = "st,stm32-timer-counter"; > > > > > > Is there only 1? How is the counter addressed? > > > > Yes there is only one counter per hardware block. > > Counter is addressed like the two others sub-nodes and the details > > about parent mode are describe in stm32-timers.txt > > Should I add them here too ? so example will be like that: > > No, you should drop the child node and add pinctrl to the parent. > > Any other functions this block has that you plan on adding? Please make > bindings as complete as possible, not what you currently have drivers > for. > > > timers@40010000 { > > #address-cells = <1>; > > #size-cells = <0>; > > compatible = "st,stm32-timers"; > > reg = <0x40010000 0x400>; > > clocks = <&rcc 0 160>; > > clock-names = "int"; > > counter { > > compatible = "st,stm32-timer-counter"; > > pinctrl-names = "default"; > > pinctrl-0 = <&tim1_in_pins>; > > }; > > }; > > > > Benjamin > > > > > > _______________________________________________ > > > linux-arm-kernel mailing list > > > linux-arm-kernel@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel