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[209.132.180.67]) by mx.google.com with ESMTP id f4-v6si6768256pgc.551.2018.05.20.10.03.59; Sun, 20 May 2018 10:04:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751725AbeETRC2 (ORCPT + 99 others); Sun, 20 May 2018 13:02:28 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:7183 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751685AbeETRCU (ORCPT ); Sun, 20 May 2018 13:02:20 -0400 X-UUID: 51cd62e6a8a2491588ef01900f521f7f-20180521 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 458288412; Mon, 21 May 2018 01:02:12 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 21 May 2018 01:02:11 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 21 May 2018 01:02:11 +0800 From: To: , , , , , CC: , , , Sean Wang Subject: [PATCH v1 1/7] dt-bindings: pinctrl: add external interrupt support to MT7622 pinctrl Date: Mon, 21 May 2018 01:01:47 +0800 Message-ID: <3898620ef606004aaddc332591ca467f56773029.1526835466.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sean Wang Extend the capability of MT7622 pinctrl with adding EINT so that each GPIO can be used to notify CPU when a signal state is changing on the line as an external interrupt. Signed-off-by: Sean Wang --- Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt index f18ed99..743b32d 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt @@ -9,6 +9,16 @@ Required properties for the root node: - #gpio-cells: Should be two. The first cell is the pin number and the second is the GPIO flags. +Optional properties: +- interrupt-controller : Marks the device node as an interrupt controller + +If the property interrupt-controller is defined, following property is required +- reg-names: A string describing the "reg" entries. Must contain "eint". +- interrupts : The interrupt output from the controller. +- #interrupt-cells: Should be two. +- interrupt-parent: Phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". -- 2.7.4