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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=+yI5JDlhd0wsXiM8bmi3YWpOwO7hG7zNdRt3fI5Nv9s=; b=BRN/W+BEgnsnA2DjM2T/hIyTF6vtT66p/n/r7Hj1l3dERBhEMYW2v0m8LvNeua6qdX Rk4ByE53yK/Gp+MV/bF26liVPICYxEeuDCrE9N5M+G60hFg8jXUDw2zAwuZhfz5cw8U0 oWqCLz3SXQ6xOksMq1fvtR8NrauUBKvqHwLw2KJECrHC8yGSehE0SoukteXoKtjY104x c3aBssuYikM3Hu8XwTcIlgduq9lSZOP2tG4a3Za0NM0DwA/Wca8m6nZzc3pusVm5zZDf MqGS5RnFbdQdTU5RKewSJXaX9NtxOJBN7MK2ehFxstR58ZHntp2wMGr9vIVZBGh/TL6E TzsQ== X-Gm-Message-State: ALKqPwfJXjEEINMY+Al6x52/WN2rrJvQtx1Ya5vShPYwAJnv/4gnZgvC N9iQS1oEEB79yA761+oIQ/Jugs140pqheB4PCnw= X-Received: by 2002:ac8:2bb8:: with SMTP id m53-v6mr17207439qtm.340.1526877237224; Sun, 20 May 2018 21:33:57 -0700 (PDT) MIME-Version: 1.0 Received: by 10.200.24.79 with HTTP; Sun, 20 May 2018 21:33:36 -0700 (PDT) In-Reply-To: <1526633822-17138-1-git-send-email-mine260309@gmail.com> References: <1526633822-17138-1-git-send-email-mine260309@gmail.com> From: Joel Stanley Date: Mon, 21 May 2018 14:03:36 +0930 X-Google-Sender-Auth: cbTrqK__Re9bMdpidLUn6jF5OA0 Message-ID: Subject: Re: [PATCH] clk: aspeed: Add 24MHz fixed clock To: Lei YU Cc: Michael Turquette , Stephen Boyd , Andrew Jeffery , Rob Herring , Mark Rutland , linux-clk@vger.kernel.org, Linux ARM , linux-aspeed@lists.ozlabs.org, Linux Kernel Mailing List , devicetree Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18 May 2018 at 18:27, Lei YU wrote: > Add a 24MHz fixed clock. > This clock will be used for certain devices, e.g. pwm. > > Signed-off-by: Lei YU Reviewed-by: Joel Stanley Cheers, Joel > --- > drivers/clk/clk-aspeed.c | 9 ++++++++- > include/dt-bindings/clock/aspeed-clock.h | 1 + > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c > index 5eb50c3..4664088 100644 > --- a/drivers/clk/clk-aspeed.c > +++ b/drivers/clk/clk-aspeed.c > @@ -14,7 +14,7 @@ > > #include > > -#define ASPEED_NUM_CLKS 35 > +#define ASPEED_NUM_CLKS 36 > > #define ASPEED_RESET_CTRL 0x04 > #define ASPEED_CLK_SELECTION 0x08 > @@ -474,6 +474,13 @@ static int aspeed_clk_probe(struct platform_device *pdev) > return PTR_ERR(hw); > aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; > > + /* Fixed 24MHz clock */ > + hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin", > + 0, 24000000); > + if (IS_ERR(hw)) > + return PTR_ERR(hw); > + aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; > + > /* > * TODO: There are a number of clocks that not included in this driver > * as more information is required: > diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h > index d3558d8..ff29d8e 100644 > --- a/include/dt-bindings/clock/aspeed-clock.h > +++ b/include/dt-bindings/clock/aspeed-clock.h > @@ -38,6 +38,7 @@ > #define ASPEED_CLK_MAC 32 > #define ASPEED_CLK_BCLK 33 > #define ASPEED_CLK_MPLL 34 > +#define ASPEED_CLK_24M 35 > > #define ASPEED_RESET_XDMA 0 > #define ASPEED_RESET_MCTP 1 > -- > 2.7.4 >