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[209.132.180.67]) by mx.google.com with ESMTP id 31-v6si15834942pli.404.2018.05.22.00.59.11; Tue, 22 May 2018 00:59:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pZE7gAtP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752065AbeEVH5f (ORCPT + 99 others); Tue, 22 May 2018 03:57:35 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:40882 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751189AbeEVH5c (ORCPT ); Tue, 22 May 2018 03:57:32 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w4M7vESS015259; Tue, 22 May 2018 02:57:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1526975834; bh=gBYIPDCG6Uq3j5lw1piI2xwfwkwc2pcNdafKz6m+zaU=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=pZE7gAtPqbn1MrkYuXTdniF0146ceH0nEzDZ63SE3sP9D3PY0PIvirwKhticqGEzk VLOy6z66+pfL+KazqTgmBJUNQAk4ez4hBJrs1Pzo6RdzRBZqqAsdALY+RfnLM4OFTi YdMXsto5KdyyZ+QjiQbaHw5f9axW+MbmhZPcFQ5o= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4M7vEhN026923; Tue, 22 May 2018 02:57:14 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 22 May 2018 02:57:14 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 22 May 2018 02:57:14 -0500 Received: from [172.24.191.45] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4M7vAwv025827; Tue, 22 May 2018 02:57:11 -0500 Subject: Re: [PATCH 12/14] OMAP: CLK: CLKSRC: Add suspend resume hooks To: Tony Lindgren CC: , , , , , , , , , References: <1523505239-16229-1-git-send-email-j-keerthy@ti.com> <1523505239-16229-13-git-send-email-j-keerthy@ti.com> <20180412142714.GX5700@atomide.com> From: Keerthy Message-ID: <038cc2cd-ff72-c9c9-257b-1c1cc09a66a8@ti.com> Date: Tue, 22 May 2018 13:27:10 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20180412142714.GX5700@atomide.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday 12 April 2018 07:57 PM, Tony Lindgren wrote: > * Keerthy [180412 03:56]: >> Add the save and restore for clksrc as part of suspend and resume >> so that it saves the counter value and restores. This is needed in >> modes like rtc+ddr in self-refresh not doing this stalls the time. > > I suspect this too should really happen with cpu_pm. I believe going by the previous set of patches this fits better with suspend/resume? > >> --- a/arch/arm/mach-omap2/timer.c >> +++ b/arch/arm/mach-omap2/timer.c >> @@ -442,6 +442,38 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void) >> return ret; >> } >> >> +static unsigned int omap2_gptimer_clksrc_load; >> + >> +static void omap2_gptimer_clksrc_suspend(struct clocksource *unused) >> +{ >> + struct omap_hwmod *oh; >> + >> + omap2_gptimer_clksrc_load = >> + __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED); >> + >> + oh = omap_hwmod_lookup(clocksource_gpt.name); >> + if (!oh) >> + return; >> + >> + omap_hwmod_idle(oh); >> +} > > Probably no need to look up the hwmod every time? Especially if am437x > will start supporting deeper idle modes during runtime. Like clockevent i will store the hwmod pointer for clocksource as well. > > And probably the cpu_pm notifies should be directly in the hwmod > code so we don't need to add more any more dependencies to hwmod > functions to timer code. We should have this code move to drivers > anyways at some point. > > Regards, > > Tony >