Date: Mon, 1 Sep 2003 06:58:04 +0100
From: Jamie Lokier <jamie@shareable.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Linux Kernel Development <linux-kernel@vger.kernel.org>
Subject: Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this
Message-ID: <20030901055804.GG748@mail.jlokier.co.uk>
References: <20030829053510.GA12663@mail.jlokier.co.uk> <Pine.GSO.4.21.0308291820540.3919-100000@waterleaf.sonytel.be>
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Geert Uytterhoeven wrote:
> Are you also interested in m68k? ;-)
> 
> cassandra:/tmp# time ./test
> Test separation: 4096 bytes: FAIL - store buffer not coherent

Especially!  I hadn't expected to see any machine that would print
"store buffer not coherent".  It means that if there's an L1 cache, it
is coherent, but any store-then-load bypass in the CPU pipeline is
using the virtual address with no rollback after MMU translation.

I had thought it would only be the case with chips using an external
MMU, but now that I think about it, the older simpler chips aren't
going to bother with things like pipeline rollback wherever they can
get away without it!

(The other CPU that is reporting "store buffer not coherent" is
PA-RISC, which is even more of an eye opener.  That has a big 1MiB
coherent L1 cache, and the pipeline bypass is coherent for very large
separations but not others!)

Thanks,
-- Jamie
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