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[209.132.180.67]) by mx.google.com with ESMTP id e6-v6si12721993pgr.374.2018.05.22.04.25.44; Tue, 22 May 2018 04:26:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=JHeaMutG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751391AbeEVLZi (ORCPT + 99 others); Tue, 22 May 2018 07:25:38 -0400 Received: from mail-oi0-f66.google.com ([209.85.218.66]:36724 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751114AbeEVLZf (ORCPT ); Tue, 22 May 2018 07:25:35 -0400 Received: by mail-oi0-f66.google.com with SMTP id v2-v6so15842761oif.3; Tue, 22 May 2018 04:25:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=AWezolYIHG26CmS7i6NWFDc/WyTbSl48y9eazphJbSk=; b=JHeaMutGiQLuzvPBrF9uJT9JuaLADUKEakcEi9FREZvQgSW5st1KOUaBl7zFcxnAfk s7ZdiXNBN7Sx2sVaNWUp6WIgXYXJUhrR3q69lbYU1J/231k7dIhFwR5nb1XfqMd697d6 XQy3H/bLn09K1lHmDgGdnEV/tHlEqqTtgAfLnc3FaQJU4MRqA9UE/JJXLZxR/R83F8o6 GArbrkeJpp5V3E8h4sfgw4wIW9SEagKaF/qt7xbvihbqS0rnyDf20iDnU3tJ0ZioWV8d LSKZAoV7ZowWZ20kbz/s+Wldv55mTT1AGgk/o4AR0sm5JR/Whz5UHRVSwg1W/svDWRzx WA+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=AWezolYIHG26CmS7i6NWFDc/WyTbSl48y9eazphJbSk=; b=KD/n0jrAr0gkSmILe7ncN795X7tpat1X2kIC59B06M8lyFenmCg28Hw8yXQ5vHbWoX Q6U8Jk8gT06vQo0SH0k+bcFncnQcnkzI2TXarftD2Euwvy5Hp67E7GLvmGl/NStw2/4M bH/F7FEGfXYvrQXZKqfi96TRXF0iCHU1orwlwF9QKLf2goQOvf0tIdmuggdAlQH0U5pL 8/mrLDN3vrIVmEuLc1VqmK+QBuX+IFUVP2U17poHrwug5olDtBEGuWd6tMjRPCN8Saju eDzJDkkgmtxw8WFPluQHXwd4uY42dGwdEhj2YCSoD8M7OewgWTNs6B8xZgH4CE05mCOP Bqqg== X-Gm-Message-State: ALKqPwcwpapu8Xrgdd0Y4amYSYYtXy3o9AcTpwbP6E7yPPYwoffv12wz bucgJxhbdXl3NTy4Q1wpOTTEnAQhsTZU1PBh+4w= X-Received: by 2002:aca:bc05:: with SMTP id m5-v6mr12053765oif.147.1526988334572; Tue, 22 May 2018 04:25:34 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a9d:4c14:0:0:0:0:0 with HTTP; Tue, 22 May 2018 04:25:34 -0700 (PDT) In-Reply-To: <1526959560-6014-1-git-send-email-Anson.Huang@nxp.com> References: <1526959560-6014-1-git-send-email-Anson.Huang@nxp.com> From: Fabio Estevam Date: Tue, 22 May 2018 08:25:34 -0300 Message-ID: Subject: Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates To: Anson Huang Cc: Shawn Guo , Sascha Hauer , Fabio Estevam , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Michael Trimarchi , Matteo Lisi , NXP Linux Team , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-kernel , linux-clk Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 22, 2018 at 12:25 AM, Anson Huang wrote: > i.MX6UL has GPIO clock gates in CCM CCGR, add > them into clock tree for clock management. > > Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam