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[24.4.232.46]) by smtp.gmail.com with ESMTPSA id j11-v6sm30600602pff.64.2018.05.22.07.37.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 May 2018 07:37:17 -0700 (PDT) Date: Tue, 22 May 2018 07:37:15 -0700 From: Richard Cochran To: "Y.b. Lu" Cc: Madalin-cristian Bucur , Claudiu Manoil , Xiaobo Xie , "linux-kernel@vger.kernel.org" Subject: Re: PTP clock driver for FSL DPAA Message-ID: <20180522143715.7um4fot2zfowkbm2@localhost> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 22, 2018 at 10:07:20AM +0000, Y.b. Lu wrote: > I'm going to make a PTP clock driver patch for FSL DPAA ethernet controller. (drivers/net/ethernet/freescale/dpaa/) > Actually the 1588 timer module on FSL DPAA is same with the one on FSL eTSEC in hardware.(whose PTP clock driver is drivers/net/ethernet/freescale/gianfar_ptp.c) > > So there are two options for me I think. > Option #1, just make a dpaa_ptp.c driver which will be almost same with gianfar_ptp.c. > Option #2, try to reuse gianfar_ptp.c driver by reworking it as a common driver, renaming it, and putting it to a common place (drivers/ptp/ or still drivers/net/ethernet/freescale/). If you can make it work, #2 sounds like the best solution. Thanks, Richard