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[209.132.180.67]) by mx.google.com with ESMTP id b18-v6si5090458pgs.668.2018.05.22.08.53.28; Tue, 22 May 2018 08:53:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751453AbeEVPvw (ORCPT + 99 others); Tue, 22 May 2018 11:51:52 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:37935 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751272AbeEVPvq (ORCPT ); Tue, 22 May 2018 11:51:46 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w4MFiYnK028662; Tue, 22 May 2018 17:51:07 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2j2ater1yu-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 22 May 2018 17:51:07 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DC7C431; Tue, 22 May 2018 15:51:05 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A9DF34FE2; Tue, 22 May 2018 15:51:05 +0000 (GMT) Received: from [10.48.0.167] (10.75.127.45) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 22 May 2018 17:51:04 +0200 Subject: Re: [PATCH v2 3/3] ARM: dts: stm32: Add ADC support to stm32mp157c To: Jonathan Cameron , CC: , , , , , , , , , , References: <1525247091-18143-1-git-send-email-fabrice.gasnier@st.com> <1525247091-18143-4-git-send-email-fabrice.gasnier@st.com> <20180507182317.7406c682@archlinux> From: Fabrice Gasnier Message-ID: Date: Tue, 22 May 2018 17:51:04 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180507182317.7406c682@archlinux> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG6NODE2.st.com (10.75.127.17) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-05-22_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/07/2018 07:23 PM, Jonathan Cameron wrote: > On Wed, 2 May 2018 09:44:51 +0200 > Fabrice Gasnier wrote: > >> stm32mp157c has an ADC block with two physical ADCs. >> >> Signed-off-by: Fabrice Gasnier > The driver support is now queued up in the IIO tree and should > be in Linux next later this week. Hi, Many Thanks Jonathan :-) Alex, I just sent an updated version (v3) of this patch (with additional dmas). Best Regards, Fabrice > > Thanks, > > Jonathan > >> --- >> arch/arm/boot/dts/stm32mp157c.dtsi | 32 ++++++++++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi >> index bc3eddc..7758a90 100644 >> --- a/arch/arm/boot/dts/stm32mp157c.dtsi >> +++ b/arch/arm/boot/dts/stm32mp157c.dtsi >> @@ -160,6 +160,38 @@ >> status = "disabled"; >> }; >> >> + adc: adc@48003000 { >> + compatible = "st,stm32mp1-adc-core"; >> + reg = <0x48003000 0x400>; >> + interrupts = , >> + ; >> + clocks = <&rcc ADC12>, <&rcc ADC12_K>; >> + clock-names = "bus", "adc"; >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + >> + adc1: adc@0 { >> + compatible = "st,stm32mp1-adc"; >> + #io-channel-cells = <1>; >> + reg = <0x0>; >> + interrupt-parent = <&adc>; >> + interrupts = <0>; >> + status = "disabled"; >> + }; >> + >> + adc2: adc@100 { >> + compatible = "st,stm32mp1-adc"; >> + #io-channel-cells = <1>; >> + reg = <0x100>; >> + interrupt-parent = <&adc>; >> + interrupts = <1>; >> + status = "disabled"; >> + }; >> + }; >> + >> rcc: rcc@50000000 { >> compatible = "st,stm32mp1-rcc", "syscon"; >> reg = <0x50000000 0x1000>; >