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[24.223.123.72]) by smtp.gmail.com with ESMTPSA id w4-v6sm7302176ywc.84.2018.05.22.11.02.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 May 2018 11:02:39 -0700 (PDT) Date: Tue, 22 May 2018 13:02:38 -0500 From: Rob Herring To: djw@t-chip.com.cn Cc: linux-rockchip@lists.infradead.org, Wayne Chou , Heiko Stuebner , devicetree@vger.kernel.org, Linus Walleij , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 2/5] gpio: syscon: Add gpio-syscon for rockchip Message-ID: <20180522180238.GA7328@rob-hp-laptop> References: <1526614328-6869-1-git-send-email-djw@t-chip.com.cn> <1526615528-9707-1-git-send-email-djw@t-chip.com.cn> <1526615528-9707-2-git-send-email-djw@t-chip.com.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1526615528-9707-2-git-send-email-djw@t-chip.com.cn> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, May 18, 2018 at 11:52:05AM +0800, djw@t-chip.com.cn wrote: > From: Levin Du > > Some GPIOs sit in the GRF_SOC_CON registers of Rockchip SoCs, > which do not belong to the general pinctrl. > > Adding gpio-syscon support makes controlling regulator or > LED using these special pins very easy by reusing existing > drivers, such as gpio-regulator and led-gpio. > > Signed-off-by: Levin Du > > --- > > Changes in v2: > - Rename gpio_syscon10 to gpio_mute in doc > > Changes in v1: > - Refactured for general gpio-syscon usage for Rockchip SoCs. > - Add doc rockchip,gpio-syscon.txt > > .../bindings/gpio/rockchip,gpio-syscon.txt | 41 ++++++++++++++++++++++ > drivers/gpio/gpio-syscon.c | 30 ++++++++++++++++ > 2 files changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt > > diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt b/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt > new file mode 100644 > index 0000000..b1b2a67 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt > @@ -0,0 +1,41 @@ > +* Rockchip GPIO support for GRF_SOC_CON registers > + > +Required properties: > +- compatible: Should contain "rockchip,gpio-syscon". > +- gpio-controller: Marks the device node as a gpio controller. > +- #gpio-cells: Should be two. The first cell is the pin number and > + the second cell is used to specify the gpio polarity: > + 0 = Active high, > + 1 = Active low. There's no need for this child node. Just make the parent node a gpio controller. Rob