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[209.132.180.67]) by mx.google.com with ESMTP id e8-v6si2512361pgu.511.2018.05.22.23.54.16; Tue, 22 May 2018 23:54:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=HbJmWheg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754195AbeEWGw7 (ORCPT + 99 others); Wed, 23 May 2018 02:52:59 -0400 Received: from mail-io0-f195.google.com ([209.85.223.195]:40163 "EHLO mail-io0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753985AbeEWGw5 (ORCPT ); Wed, 23 May 2018 02:52:57 -0400 Received: by mail-io0-f195.google.com with SMTP id g14-v6so21501355ioc.7; Tue, 22 May 2018 23:52:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=qtN2Cac4twpUVnejvD2Do66WM7Vd6phd/6kr17bbsXc=; b=HbJmWhegh+BJacrq1ljlY+ptDNOL/b18JdTa452iyCQZ/XwWHVp8b8KkBKp9xRX5d/ MI6F8es2enuBWtoHq9QBkh6g9ajjFY/HvFYzQRH36VGYHbRlBjQDUEe6sz1tn5UdQsmT E5ImYxnWuxXbwZZycT7/OS+5yomGcOCG5WDnKYlqsNFkQLjxePZ1oXfefsp4rd5MB5QQ Qr9GgVLJEd0871oyLbSv7z80gGjoSueh7KLKwNjztw+68eElDrtDvFwPxVsJRwpqYR/q WN/s3K+mNiHWlFXCsPe7B7iSdypfRD8nBd25LfIHuoQxC73ZI9Go/q46jPdb09HNctL7 c0jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=qtN2Cac4twpUVnejvD2Do66WM7Vd6phd/6kr17bbsXc=; b=cEKDaL3WCedCsyRi9EO5LjP6E4HPyj7iasskloOIpoN63TSda3cUSzHEJy+Unr1adC Rw3W+mAMd5ikWqyhM6SF+0v4DNEIER9BfsD/CkJuJZ2LpsONjD8KQe0ncDn8FPCz6la0 TSSRzdcM4qfaOsmAB1qweNGDh08NqeyycIYtQPpMbVjirdPJtSa0Hx5Lz1/zcKeNuOTN M70wnznN+Umsl0zjXXzgUtcmnl3/yfwB5R0gjpKKwMkwkWjGnlitNd1OOHhYF8ygeq7y D0KEG0lKgwTfBc/Cwtox1bW7rqJdangriV/5ecmJxWdkuOOGX8FfnDKQi2SoDRmFMdKc URMw== X-Gm-Message-State: ALKqPwf2wduK2J5gXBvTBUnN/h8wP4pXQSdCcH7qDHD4QC8HGKYOkKCU iPGLC1MnSdM8t4BC6v1TPw/mNe7rd+juNEgozBI= X-Received: by 2002:a5e:c001:: with SMTP id u1-v6mr1347891iol.10.1527058376629; Tue, 22 May 2018 23:52:56 -0700 (PDT) MIME-Version: 1.0 References: <1526983321-41949-1-git-send-email-michel.pollet@bp.renesas.com> <1526983321-41949-4-git-send-email-michel.pollet@bp.renesas.com> <20180522160913.GA7755@rob-hp-laptop> In-Reply-To: <20180522160913.GA7755@rob-hp-laptop> From: M P Date: Wed, 23 May 2018 07:52:45 +0100 Message-ID: Subject: Re: [PATCH v6 3/6] dt-bindings: clock: renesas,rzn1-clocks: document RZ/N1 clock driver To: robh@kernel.org Cc: michel.pollet@bp.renesas.com, linux-renesas-soc@vger.kernel.org, horms@verge.net.au, Phil Edworthy , buserror+upstream@gmail.com, magnus.damm@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, sboyd@kernel.org, geert+renesas@glider.be, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, On Tue, 22 May 2018 at 17:09, Rob Herring wrote: > On Tue, May 22, 2018 at 11:01:23AM +0100, Michel Pollet wrote: > > The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver > > to provide the SoC clock infrastructure for Linux. > > > > This documents the driver bindings. > > > > Signed-off-by: Michel Pollet > > --- > > .../bindings/clock/renesas,rzn1-clocks.txt | 44 ++++++++++++++++++++++ > > 1 file changed, 44 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt > > > > diff --git a/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt > > new file mode 100644 > > index 0000000..0c41137 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt > > @@ -0,0 +1,44 @@ > > +* Renesas RZ/N1 Clock Driver > > + > > +This driver provides the clock infrastructure used by all the other drivers. > Bindings document h/w not drivers. > > + > > +One of the 'special' feature of this infrastructure is that Linux doesn't > Bindings are not just for Linux. > > +necessary 'own' all the clocks on the SoC, some other OS runs on > > +the Cortex-M3 core and that OS can access and claim it's own clocks. > How is this relevant to the binding? Well you just said it, if the binding is not just for linux, it's probably a good idea to mention it somewhere since I can promise you it's *not* documented in the hardware manual. Whatever this binding is for, it's relevant to point out it is different from the other clock drivers in the same directory... ? > > + > > +Required Properties: > > + > > + - compatible: Must be > > + - "renesas,r9a06g032-clocks" for the RZ/N1D > > + and "renesas,rzn1-clocks" as a fallback. > Is "clocks" how the chip reference manual refers to this block? No, the block is called 'sysctrl' and has tons of other stuff in there. I've tried multiple times to get a 'sysctrl' driver in the previous versions of the patch, in various shape or form, and I can't because I'd be supposed to 'document' binding for stuff that has no code, no purpose, no testing, and have all wildly different topics. So, after some more lengthily discussion with Geert, we've decided to make the 'primary' feature of that block (clocks) as a driver, and see from there onward. Thanks for all the other comments, all taken onboard for next version! Michel > > + - reg: Base address and length of the memory resource used by the driver > > + - #clock-cells: Must be 1 > > + > > +Examples > > +-------- > > + > > + - Clock driver device node: > > + > > + clock: clocks@4000c000 { > clock-controller@... > > + compatible = "renesas,r9a06g032-clocks", > > + "renesas,rzn1-clocks"; > > + reg = <0x4000c000 0x1000>; > > + status = "okay"; > Don't show status in examples. (Plus, I doubt you ever want to have this > disabled, so you don't need the property in your dts files either). > > + #clock-cells = <1>; > > + }; > > + > > + > > + - Other drivers can use the clocks as in: > s/drivers/nodes/ > > + > > + uart0: serial@40060000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0x40060000 0x400>; > > + interrupts = ; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + clocks = <&clock RZN1_CLK_UART0>; > > + clock-names = "baudclk"; > > + }; > > + Note the use of RZN1_CLK_UART0 -- these constants are declared in > > + the rzn1-clocks.h header file. These are not hardware based constants > > + and are Linux specific. > No, they are not Linux specific. They are part of the DT ABI. > While it is not a requirement to base them on some h/w numbering, it is > preferred if you can. That usually only works if you can base them on > bit positions or register offsets. > Rob