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[209.132.180.67]) by mx.google.com with ESMTP id h10-v6si11640824pgq.131.2018.05.23.02.21.05; Wed, 23 May 2018 02:21:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=bJOVlWT1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932184AbeEWJUp (ORCPT + 99 others); Wed, 23 May 2018 05:20:45 -0400 Received: from mail-it0-f68.google.com ([209.85.214.68]:55259 "EHLO mail-it0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932128AbeEWJUc (ORCPT ); Wed, 23 May 2018 05:20:32 -0400 Received: by mail-it0-f68.google.com with SMTP id z6-v6so3505820iti.4; Wed, 23 May 2018 02:20:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=kwT6e+5tF7vNq6Mv3ZfiZDINDJ2OQPF2xrTbvsIPXZM=; b=bJOVlWT1VXHqVfA/BVQVLneqoGzHlI25Rx4RXkHiRlil/CRAk12wqpvMLTI9Igq03x tlot501JL8X+61JbbOZzVTEp2nuN08T6ivRYeS+vHxH0j2fkN5CRtdzo5ymDzSIwfNES Yh0bOwdh3Q7XqfJSkqiE4PnJljoVFzpKrdkKZmcpS6ySgJxth/rHruEZBnZ1Z12dbMa3 ksiJA5tyrgO2tFLKZtrMsYMbwySu9E6YhQyx9pQXHgEENogTkUsZBeHRFTzCztdYMo/g 5TNYg87R4QTmqlXxZ8dg650+9W131C5OqC05nd+xB6AxzXDro9qnXWG1zuEl3BLk22bE MBsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kwT6e+5tF7vNq6Mv3ZfiZDINDJ2OQPF2xrTbvsIPXZM=; b=CemI7ohdpPeFj2sZhv4e6b0KfjpXfkb7YrowJkNo6UL1YhpGPGi5AZhgp1iOEwFTGg eZkm3Y+Yk7LIBNoio2V7EBMiwrloCPidM4jBdjNwn41yKKirclF9wOy5n0iFXFDYkiJt AmlQML7S0T5mWnaWfaMALXhaRQe42aTqOPNMdDApC4/PCBbWPeKxOdSsHUc1u/3iJB96 jPc8O0DSpzEWbDzMeXMmY2SHczTvULYECzMQbCjB/90JYwQKGKjXD5OKfGWaVN/UQ3t2 W7Er6zIjZlsZLLh0E0BvxBrERZ6nB+XcI6go4nFbCVr2Rbx9Pu4W6fSsgSfg4YsGxqzR xX+w== X-Gm-Message-State: ALKqPweibLOPegdc01P08/ugyXXUWCcA9OaYRevejhMJXyOvrTSanMEP RGK3wg1LntAj9XDTEiw9DFj0JvHuxJahOAUCO9I= X-Received: by 2002:a24:4d8d:: with SMTP id l135-v6mr4288313itb.142.1527067231147; Wed, 23 May 2018 02:20:31 -0700 (PDT) MIME-Version: 1.0 References: <1526983321-41949-1-git-send-email-michel.pollet@bp.renesas.com> <1526983321-41949-5-git-send-email-michel.pollet@bp.renesas.com> In-Reply-To: From: M P Date: Wed, 23 May 2018 10:20:20 +0100 Message-ID: Subject: Re: [PATCH v6 4/6] ARM: dts: Renesas RZ/N1 SoC base device tree file To: Geert Uytterhoeven Cc: michel.pollet@bp.renesas.com, linux-renesas-soc@vger.kernel.org, Simon Horman , Phil Edworthy , buserror+upstream@gmail.com, Magnus Damm , robh+dt@kernel.org, mark.rutland@arm.com, Michael Turquette , sboyd@kernel.org, geert+renesas@glider.be, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Geert, On Wed, 23 May 2018 at 10:12, Geert Uytterhoeven wrote: > Hi Michel, > On Tue, May 22, 2018 at 12:01 PM, Michel Pollet > wrote: > > This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare > > bone support. > > > > This currently only handles generic parts (gic, architected timer) > > and a UART. > > For simplicity sake, this also relies on the bootloader to set the > > pinctrl and clocks. > > > > Signed-off-by: Michel Pollet > Thanks for your patch! > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&clock RZN1_DIV_CA7>; > I think the clocks property should be moved to the individual CPU nodes. Ah, I had a look around, and I found some instances that are in the cpu sub-node, and others that are not -- it seems that having it in the cpu sub-node would implies it's core specific... here if that clock is changed both cores would change speed... Either way, it's not used by the kernel in any way at the moment -- I had hoped cpufreq or something would claim it, but it's not the case. Thanks, Michel