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[209.132.180.67]) by mx.google.com with ESMTP id e2-v6si21219260pfm.220.2018.05.24.01.01.13; Thu, 24 May 2018 01:02:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=bd6Ue/HQ; dkim=pass header.i=@codeaurora.org header.s=default header.b=ITl6au+u; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965307AbeEXHvC (ORCPT + 99 others); Thu, 24 May 2018 03:51:02 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:54312 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965274AbeEXHu5 (ORCPT ); Thu, 24 May 2018 03:50:57 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A350060FA9; Thu, 24 May 2018 07:50:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527148256; bh=wFVifI9YZTHt6bXghKA3d9bD6PaJjaPNLQI8GRZk3hU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bd6Ue/HQf7kxVSCKYTx0by4thJf9+0PwY4aoiXffVxghTc66N/nscE5yaYHtEQXrz O00H7PhufU5JiAGF+zeK25SYUfEi9ziVFiZasSxr4lt7DBAOkWE+fZDAZqfClwXY+Z gKxtXTDJwTRHJaphoUOirJCF/eHTMGa7595vwXCQ= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from lx-ilial.mea.qualcomm.com (unknown [185.23.60.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilialin@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B46C260F92; Thu, 24 May 2018 07:50:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527148255; bh=wFVifI9YZTHt6bXghKA3d9bD6PaJjaPNLQI8GRZk3hU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ITl6au+uxiHF5lUcOV641RskXY1SSFwgBKo9HV9H8FlBdI4W92qajqxOQVR9qA9pq zu/lH+3Xk4MdBthB1g3aw8phT8nmuEbs0IO7DgrqLL36/R6B0aVVU3p/sMK2mmyv1w kT/0AkgzK1ImqxaFGV6939XIi3c1o1q2WEnOw/i0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B46C260F92 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilialin@codeaurora.org From: Ilia Lin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, will.deacon@arm.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, vireshk@kernel.org, ilialin@codeaurora.org Subject: [PATCH v12 8/8] clk: qcom: Add ACD path to CPU clock driver for msm8996 Date: Thu, 24 May 2018 10:50:18 +0300 Message-Id: <1527148218-16540-9-git-send-email-ilialin@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527148218-16540-1-git-send-email-ilialin@codeaurora.org> References: <1527148218-16540-1-git-send-email-ilialin@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PMUX for each duplex allows for selection of ACD clock source. The DVM (Dynamic Variation Monitor) will flag an error when a voltage droop event is detected. This flagged error enables ACD to provide a div-by-2 clock, sourced from the primary PLL. The duplex will be provided the divided clock until a pre-programmed delay has expired. This change configures ACD during the probe and switches the PMUXes to the ACD clock source. Signed-off-by: Ilia Lin --- drivers/clk/qcom/clk-cpu-8996.c | 75 +++++++++++++++++++++++++++++++++++------ 1 file changed, 65 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index ff5c0a5..0a908d8 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -53,9 +53,11 @@ */ #include +#include #include #include #include +#include #include "clk-alpha-pll.h" #include "clk-regmap.h" @@ -69,6 +71,11 @@ enum _pmux_input { }; #define DIV_2_THRESHOLD 600000000 +#define PWRCL_REG_OFFSET 0x0 +#define PERFCL_REG_OFFSET 0x80000 +#define MUX_OFFSET 0x40 +#define ALT_PLL_OFFSET 0x100 +#define SSSCTL_OFFSET 0x160 static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { [PLL_OFF_L_VAL] = 0x04, @@ -107,7 +114,7 @@ enum _pmux_input { }; static struct clk_alpha_pll perfcl_pll = { - .offset = 0x80000, + .offset = PERFCL_REG_OFFSET, .regs = prim_pll_regs, .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ @@ -119,7 +126,7 @@ enum _pmux_input { }; static struct clk_alpha_pll pwrcl_pll = { - .offset = 0x0, + .offset = PWRCL_REG_OFFSET, .regs = prim_pll_regs, .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ @@ -149,7 +156,7 @@ enum _pmux_input { }; static struct clk_alpha_pll perfcl_alt_pll = { - .offset = 0x80100, + .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET, .regs = alt_pll_regs, .vco_table = alt_pll_vco_modes, .num_vco = ARRAY_SIZE(alt_pll_vco_modes), @@ -163,7 +170,7 @@ enum _pmux_input { }; static struct clk_alpha_pll pwrcl_alt_pll = { - .offset = 0x100, + .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET, .regs = alt_pll_regs, .vco_table = alt_pll_vco_modes, .num_vco = ARRAY_SIZE(alt_pll_vco_modes), @@ -176,6 +183,9 @@ enum _pmux_input { }, }; +void __iomem *base; +static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base); + /* Mux'es */ struct clk_cpu_8996_mux { @@ -253,6 +263,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, switch (event) { case PRE_RATE_CHANGE: ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); + qcom_cpu_clk_msm8996_acd_init(base); break; case POST_RATE_CHANGE: if (cnd->new_rate < DIV_2_THRESHOLD) @@ -260,7 +271,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, DIV_2_INDEX); else ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, - PLL_INDEX); + ACD_INDEX); break; default: ret = 0; @@ -276,7 +287,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, }; static struct clk_cpu_8996_mux pwrcl_smux = { - .reg = 0x40, + .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 2, .width = 2, .clkr.hw.init = &(struct clk_init_data) { @@ -292,7 +303,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, }; static struct clk_cpu_8996_mux perfcl_smux = { - .reg = 0x80040, + .reg = PERFCL_REG_OFFSET + MUX_OFFSET, .shift = 2, .width = 2, .clkr.hw.init = &(struct clk_init_data) { @@ -308,7 +319,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, }; static struct clk_cpu_8996_mux pwrcl_pmux = { - .reg = 0x40, + .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, @@ -329,7 +340,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, }; static struct clk_cpu_8996_mux perfcl_pmux = { - .reg = 0x80040, + .reg = PERFCL_REG_OFFSET + MUX_OFFSET, .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, @@ -393,6 +404,10 @@ struct clk_regmap *clks[] = { clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); + /* Enable alt PLLs */ + clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk); + clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk); + ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb); if (ret) return ret; @@ -402,10 +417,48 @@ struct clk_regmap *clks[] = { return ret; } +#define CPU_AFINITY_MASK 0xFFF +#define PWRCL_CPU_REG_MASK 0x3 +#define PERFCL_CPU_REG_MASK 0x103 + +#define L2ACDCR_REG 0x580ULL +#define L2ACDTD_REG 0x581ULL +#define L2ACDDVMRC_REG 0x584ULL +#define L2ACDSSCR_REG 0x589ULL + +static DEFINE_SPINLOCK(acd_lock); + +static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base) +{ + u64 hwid; + unsigned long flags; + + spin_lock_irqsave(&acd_lock, flags); + + hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK; + + kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006A11); + kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000E0F0F); + kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601); + + if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) { + writel(0xF, base + PWRCL_REG_OFFSET + SSSCTL_OFFSET); + wmb(); + kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002C5FFD); + } + + if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) { + kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002C5FFD); + writel(0xF, base + PERFCL_REG_OFFSET + SSSCTL_OFFSET); + wmb(); + } + + spin_unlock_irqrestore(&acd_lock, flags); +} + static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) { int ret; - void __iomem *base; struct resource *res; struct regmap *regmap; struct clk_hw_onecell_data *data; @@ -429,6 +482,8 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) if (ret) return ret; + qcom_cpu_clk_msm8996_acd_init(base); + data->hws[0] = &pwrcl_pmux.clkr.hw; data->hws[1] = &perfcl_pmux.clkr.hw; data->num = 2; -- 1.9.1