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[209.132.180.67]) by mx.google.com with ESMTP id l2-v6si16041924pgc.438.2018.05.24.01.19.02; Thu, 24 May 2018 01:19:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=dDAatHl3; dkim=pass header.i=@codeaurora.org header.s=default header.b=Q9QYT5Ew; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965135AbeEXISI (ORCPT + 99 others); Thu, 24 May 2018 04:18:08 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57890 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935821AbeEXISE (ORCPT ); Thu, 24 May 2018 04:18:04 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 02A7E60117; Thu, 24 May 2018 08:18:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527149884; bh=UyRjfdA6r1Uzm5AY/ESY4XFhEHwhQbVAr3easKAR/xg=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=dDAatHl3E0jyl+0KCTIN9zXDfiDSaJpOQ4sOLgrQKANc2Nab1JvVf5fqPaWqe3AIq Sp70IS7bsdpDiNcRVslsZZ/rFw6Qzoe3NS6G1GXBDQ5QuTSk4N13SFHmTno7YAYVgL J7ujUYk/UeTa6mJ0+iBvYtUnFSAi8p0lAjRNMIQs= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from [10.79.40.245] (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DA40960117; Thu, 24 May 2018 08:18:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527149883; bh=UyRjfdA6r1Uzm5AY/ESY4XFhEHwhQbVAr3easKAR/xg=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=Q9QYT5EwCaKRJd7hawbLefqmZaO9rM9CEx87CxK8h/VtsbBoZMromZ4EyWncmxjSJ FoQ+cYg9RCJN14vWx1SYkftUAK6DXT9yxJOi4KrAGQyPNnRjm2OvjrIeXDU9969Vb6 XG6DMWxaLMUOVfshvWq0dpmJR/n/YQzknDG/CLE4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DA40960117 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org Subject: Re: [PATCH v5 1/3] phy: Power on PHY before start Serdes configuration To: Can Guo , subhashj@codeaurora.org, asutoshd@codeaurora.org, mgautam@codeaurora.org, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20180523034712.3420-1-cang@codeaurora.org> <20180523034712.3420-2-cang@codeaurora.org> From: Vivek Gautam Message-ID: Date: Thu, 24 May 2018 13:47:58 +0530 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <20180523034712.3420-2-cang@codeaurora.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Can, On 5/23/2018 9:17 AM, Can Guo wrote: > PHYs should be powered on before register configuration starts. > > Signed-off-by: Can Guo > --- Thanks for fixing this. > drivers/phy/qualcomm/phy-qcom-qmp.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c > index 97ef942..9bfdba1 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c > @@ -1000,6 +1000,12 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp) > SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); > } > > + /* > + * Pull out PHY from POWER DOWN state. > + * This is active low enable signal to power-down PHY. > + */ > + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); > + Thanks. This is in sync with the requirements of USB and UFS phys across platforms using this qmp phy driver, viz. 8996 and 845. However, as discussed with you offline the PCIe phy has different requirement. PCIe phy on 8996 doesn't need the QPHY_POWER_DOWN_CONTROL (pcs level power down) before configuring the phys. Rather COM_POWER_DOWN_CONTROL is enough. It needs the QPHY_POWER_DOWN_CONTROL after programming the serdes, tx, rx, and pcs blocks, and right before doing SW_RESET, and START_CONTROL. So we should just do the above QPHY_POWER_DOWN_CONTROL in qcom_qmp_phy_com_init() only for non-PCIe phys at the moment, and skip the QPHY_POWER_DOWN_CONTROL in qcom_qmp_phy_init() for these non-PCIe phys. Thanks Vivek > /* Serdes configuration */ > qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl, > cfg->serdes_tbl_num);