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[209.132.180.67]) by mx.google.com with ESMTP id 64-v6si20435614pfl.309.2018.05.24.01.37.01; Thu, 24 May 2018 01:38:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965443AbeEXIfX convert rfc822-to-8bit (ORCPT + 99 others); Thu, 24 May 2018 04:35:23 -0400 Received: from gloria.sntech.de ([95.129.55.99]:60102 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965007AbeEXIfU (ORCPT ); Thu, 24 May 2018 04:35:20 -0400 Received: from ip9234b5ac.dynamic.kabel-deutschland.de ([146.52.181.172] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1fLliK-0004BO-Sy; Thu, 24 May 2018 10:35:12 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Linus Walleij Cc: Rob Herring , Levin Du , "open list:ARM/Rockchip SoC..." , Wayne Chou , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" , Mark Rutland , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Subject: Re: [PATCH v2 2/5] gpio: syscon: Add gpio-syscon for rockchip Date: Thu, 24 May 2018 10:35:12 +0200 Message-ID: <2044895.BqI5yRtle6@diego> In-Reply-To: References: <1526614328-6869-1-git-send-email-djw@t-chip.com.cn> <1685755.J6GI985WX3@diego> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="iso-8859-1" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Linus, Am Donnerstag, 24. Mai 2018, 10:28:44 CEST schrieb Linus Walleij: > On Wed, May 23, 2018 at 5:12 PM, Heiko St?bner wrote: > > So the gpio controller should definitly also be a subnode. > > > > The gpio in question is called "mute", so I'd think the gpio-syscon driver > > should just define a "rockchip,rk3328-gpio-mute" compatible and contain > > all the register voodoo in the driver itself and not define it in the dt. > > > > So it should probably look like > > > > grf: syscon at ff100000 { > > > > compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; > > > > [all the other syscon sub-devices] > > > > gpio_mute: gpio-mute { > > > > compatible = "rockchip,rk3328-gpio-mute"; > > gpio-controller; > > #gpio-cells = <2>; > > > > }; > > I'm sceptic. > > That doesn't sound like "general purpose input output" at all. > > It sounds like special purpose, for a mute button. > > Does it use IRQ? I would recommend implementing > drivers/input/keyboard/syscon-keys.c in the same vein > as drivers/leds/leds-syscon.c so you can avoid indirection > through GPIO for no good reason at all. To quote Levin from the other mail: -------- The "mute" pin is a output only GPIO, which is already supported by setting flags in the gpio-syscon driver. And yes, this pin has a defined function, but can also be used for general purpose operation. -------- So to summarize, the documentation calls it "mute", but it is usable as a general pin, which is the reason Levin is working on it - because on his board this pin is used to switch between two voltages (aka a gpio-regulator) for the sdmmc controller [3.3V + 1.8V]. Available pin settings are output-enable + of course the high/low setting and I think I remember there is even a pull setting for it in the GRF somewhere - but my memory might be fuzzy here. Heiko