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Date:   Thu, 24 May 2018 10:43:51 +0200
From:   Maxime Ripard <maxime.ripard@bootlin.com>
To:     Jernej =?utf-8?Q?=C5=A0krabec?= <jernej.skrabec@siol.net>
Cc:     wens@csie.org, robh+dt@kernel.org, mark.rutland@arm.com,
        dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH 05/15] drm/sun4i: Add TCON TOP driver
Message-ID: <20180524084351.x4ugbbsz3mqv6fh7@flea>
References: <20180519183127.2718-1-jernej.skrabec@siol.net>
 <20180519183127.2718-6-jernej.skrabec@siol.net>
 <20180521080517.3qmlfajqpn4uw7jv@flea>
 <5965231.6ucpJrPIQ5@jernej-laptop>
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Hi,

On Mon, May 21, 2018 at 05:15:15PM +0200, Jernej =C5=A0krabec wrote:
> > > +	/*
> > > +	 * Default register values might have some reserved bits set, which
> > > +	 * prevents TCON TOP from working properly. Set them to 0 here.
> > > +	 */
> > > +	writel(0, tcon_top->regs + TCON_TOP_PORT_SEL_REG);
> > > +	writel(0, tcon_top->regs + TCON_TOP_GATE_SRC_REG);
> > > +
> > > +	for (i =3D 0; i < CLK_NUM; i++) {
> > > +		const char *parent_name =3D "bus-tcon-top";
> >=20
> > I guess retrieving the parent's clock name at runtime would be more
> > flexible.
>=20
> It is, but will it ever be anything else?

Probably not, but when the complexity is exactly the same (using
__clk_get_name), we'd better use the more appropriate solution. If we
ever need to change that clock name, or to use the driver with an SoC
that wouldn't have the same clock name for whatever reason, it will
just work.

> > > +		struct clk_init_data init;
> > > +		struct clk_gate *gate;
> > > +
> > > +		gate =3D devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
> > > +		if (!gate) {
> > > +			ret =3D -ENOMEM;
> > > +			goto err_disable_clock;
> > > +		}
> > > +
> > > +		init.name =3D gates[i].name;
> > > +		init.ops =3D &clk_gate_ops;
> > > +		init.flags =3D CLK_IS_BASIC;
> > > +		init.parent_names =3D &parent_name;
> > > +		init.num_parents =3D 1;
> > > +
> > > +		gate->reg =3D tcon_top->regs + TCON_TOP_GATE_SRC_REG;
> > > +		gate->bit_idx =3D gates[i].bit;
> > > +		gate->lock =3D &tcon_top->reg_lock;
> > > +		gate->hw.init =3D &init;
> > > +
> > > +		ret =3D devm_clk_hw_register(dev, &gate->hw);
> > > +		if (ret)
> > > +			goto err_disable_clock;
> >=20
> > Isn't it what clk_hw_register_gate is doing?
>=20
> Almost, but not exactly. My goal was to use devm_* functions, so there is=
 no=20
> need to do any special cleanup.

Is it the only difference? If so, you can just create a
devm_clk_hw_register gate.

Maxime

--=20
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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