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[209.132.180.67]) by mx.google.com with ESMTP id z190-v6si16286886pgb.108.2018.05.24.01.49.08; Thu, 24 May 2018 01:49:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JYEFVWia; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965582AbeEXIsW (ORCPT + 99 others); Thu, 24 May 2018 04:48:22 -0400 Received: from mail-it0-f66.google.com ([209.85.214.66]:50646 "EHLO mail-it0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965559AbeEXIsA (ORCPT ); Thu, 24 May 2018 04:48:00 -0400 Received: by mail-it0-f66.google.com with SMTP id p3-v6so1393674itc.0 for ; Thu, 24 May 2018 01:48:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=IY7b7Gp+cdAU0gZC+gBHOCyH5CK8AmV7cKJ4vczcMUQ=; b=JYEFVWiawZkNwXfyF5DAkponw85iehV1uICBKtt610HbUOEf1utMzuo7PuhR15poBP 5JyFmZfcJrnvMj24XL3zV2dK4nWM35hRCzZkli/g1QP64Y5CXhD1o90E9RQs9QKl3To5 iuXTtKqCUaPnJ/usCJ+n5oKjdJUglnheSSJCU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=IY7b7Gp+cdAU0gZC+gBHOCyH5CK8AmV7cKJ4vczcMUQ=; b=rCWue7fYYo2ak5Mg14z8WBOzPchoyVskNoNpCADeoNwowa2m9SEUwAZu2DAWGyRoLw XSGnrB2jQSe6SgpIi25YomD8osryOye4S2fhns72PPmvgIykqnfTw+SS4kjnsSZ5EL8t i3LQ8p3hapw8lv5A6T5g82rNxcZr4nXdp7d79J31RjWfdyYbOtcB/g/hHVj8zS8FHR8k q8p9hZZYKfSA5CP8Y1I7h3mYRDcQK1scRK6B2VwWE3XNz314TfVbS2gfWU3AdQmI/rBQ ayCfCzuF9FkaVdl1DegFc+1nK/ehtgxxPJL2i4HgofpO9IerTMhBDhFrYx/GwYQXWU5G FzVA== X-Gm-Message-State: ALKqPwcw0GDndOdPVO16dKwbt0me4RW2HOb9RPa40PdemNMLLa0kc6Ox yVata5C9X1UlubdDBoJ3T8hT+x4dMGn+2KGsyiq9Gg== X-Received: by 2002:a24:c146:: with SMTP id e67-v6mr8247018itg.70.1527151680311; Thu, 24 May 2018 01:48:00 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a4f:78c9:0:0:0:0:0 with HTTP; Thu, 24 May 2018 01:47:59 -0700 (PDT) In-Reply-To: <2044895.BqI5yRtle6@diego> References: <1526614328-6869-1-git-send-email-djw@t-chip.com.cn> <1685755.J6GI985WX3@diego> <2044895.BqI5yRtle6@diego> From: Linus Walleij Date: Thu, 24 May 2018 10:47:59 +0200 Message-ID: Subject: Re: [PATCH v2 2/5] gpio: syscon: Add gpio-syscon for rockchip To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Cc: Rob Herring , Levin Du , "open list:ARM/Rockchip SoC..." , Wayne Chou , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" , Mark Rutland , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 24, 2018 at 10:35 AM, Heiko St=C3=BCbner wrot= e: > Am Donnerstag, 24. Mai 2018, 10:28:44 CEST schrieb Linus Walleij: >> On Wed, May 23, 2018 at 5:12 PM, Heiko St=C3=BCbner wr= ote: >> > So the gpio controller should definitly also be a subnode. >> > >> > The gpio in question is called "mute", so I'd think the gpio-syscon dr= iver >> > should just define a "rockchip,rk3328-gpio-mute" compatible and contai= n >> > all the register voodoo in the driver itself and not define it in the = dt. >> > >> > So it should probably look like >> > >> > grf: syscon at ff100000 { >> > >> > compatible =3D "rockchip,rk3328-grf", "syscon", "simple-mfd"; >> > >> > [all the other syscon sub-devices] >> > >> > gpio_mute: gpio-mute { >> > >> > compatible =3D "rockchip,rk3328-gpio-mute"; >> > gpio-controller; >> > #gpio-cells =3D <2>; >> > >> > }; >> >> I'm sceptic. >> >> That doesn't sound like "general purpose input output" at all. >> >> It sounds like special purpose, for a mute button. >> >> Does it use IRQ? I would recommend implementing >> drivers/input/keyboard/syscon-keys.c in the same vein >> as drivers/leds/leds-syscon.c so you can avoid indirection >> through GPIO for no good reason at all. > > To quote Levin from the other mail: > -------- > The "mute" pin is a output only GPIO, which is already supported by > setting flags in the gpio-syscon > driver. And yes, this pin has a defined function, but can also be used > for general purpose operation. > -------- > > So to summarize, the documentation calls it "mute", but it is usable as > a general pin, which is the reason Levin is working on it - because on hi= s > board this pin is used to switch between two voltages (aka a gpio-regulat= or) > for the sdmmc controller [3.3V + 1.8V]. OK then, I was wrong! :) Go ahead with this, sorry for the fuzz. Yours, Linus Walleij