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[209.132.180.67]) by mx.google.com with ESMTP id s71-v6si22681616pfi.74.2018.05.24.19.50.43; Thu, 24 May 2018 19:50:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=mcTxFycg; dkim=pass header.i=@codeaurora.org header.s=default header.b=VKAOd7L2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S972111AbeEYBci (ORCPT + 99 others); Thu, 24 May 2018 21:32:38 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:54334 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965152AbeEYBcg (ORCPT ); Thu, 24 May 2018 21:32:36 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 963C6604D4; Fri, 25 May 2018 01:32:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527211955; bh=DoraNk3F/GoJHuOFH0vK0aySQjTE5LG064A4O6bxB4k=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=mcTxFycgETJ18AoPEVoOg2d30FicaneHZYACuhtOcCqP+pSH/m853ihN1B9s96J6F 5DuMoFeVbQUOIvVHiDMSvLtd44vQdpa14owsCUn7Oopv4twbqOcglb5zlZDWb/eXwx g9VjhlC3rY+2xj8XyQc/g7Nyd/zrBwbymJoYTSmo= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id DA25460227; Fri, 25 May 2018 01:32:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527211954; bh=DoraNk3F/GoJHuOFH0vK0aySQjTE5LG064A4O6bxB4k=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=VKAOd7L24QcrXJEOGNvz3zYoxrx3UvZopH2agKMmbAQ2W3wz9VqnviD+F9iCpVaX6 e7yk78prex4S6yUvgLDjmRnqA2lkjsfxNdT4dKfs8VHgw+qC38u4yLiVt7/4PgesGI 9JzvDsbdOauhhrEWTNaNmoS+H6wIBIqfF3qIJhJE= MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Fri, 25 May 2018 09:32:34 +0800 From: cang@codeaurora.org To: Vivek Gautam Cc: subhashj@codeaurora.org, asutoshd@codeaurora.org, mgautam@codeaurora.org, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v5 1/3] phy: Power on PHY before start Serdes configuration In-Reply-To: References: <20180523034712.3420-1-cang@codeaurora.org> <20180523034712.3420-2-cang@codeaurora.org> Message-ID: <7d45dbec17a9bbf48159c6857f89a65a@codeaurora.org> X-Sender: cang@codeaurora.org User-Agent: Roundcube Webmail/1.2.5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2018-05-24 16:17, Vivek Gautam wrote: > Hi Can, > > > On 5/23/2018 9:17 AM, Can Guo wrote: >> PHYs should be powered on before register configuration starts. >> >> Signed-off-by: Can Guo >> --- > > Thanks for fixing this. > >> drivers/phy/qualcomm/phy-qcom-qmp.c | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c >> b/drivers/phy/qualcomm/phy-qcom-qmp.c >> index 97ef942..9bfdba1 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c >> @@ -1000,6 +1000,12 @@ static int qcom_qmp_phy_com_init(struct >> qcom_qmp *qmp) >> SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); >> } >> + /* >> + * Pull out PHY from POWER DOWN state. >> + * This is active low enable signal to power-down PHY. >> + */ >> + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); >> + > > Thanks. This is in sync with the requirements of USB and UFS phys > across platforms > using this qmp phy driver, viz. 8996 and 845. > However, as discussed with you offline the PCIe phy has different > requirement. > PCIe phy on 8996 doesn't need the QPHY_POWER_DOWN_CONTROL (pcs level > power down) > before configuring the phys. Rather COM_POWER_DOWN_CONTROL is enough. > It needs the QPHY_POWER_DOWN_CONTROL after programming the > serdes, tx, rx, and pcs blocks, and right before doing SW_RESET, and > START_CONTROL. > > So we should just do the above QPHY_POWER_DOWN_CONTROL in > qcom_qmp_phy_com_init() only for non-PCIe phys at the moment, and > skip the QPHY_POWER_DOWN_CONTROL in qcom_qmp_phy_init() > for these non-PCIe phys. > > Thanks > Vivek > Sure Vivek, I shall make the change per we talked. Thanks Can >> /* Serdes configuration */ >> qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl, >> cfg->serdes_tbl_num);