Received: by 2002:ac0:a594:0:0:0:0:0 with SMTP id m20-v6csp3275933imm; Fri, 25 May 2018 02:55:20 -0700 (PDT) X-Google-Smtp-Source: AB8JxZptBnboaKRA7MnNRkYbTSe6roIqCOe4AxDQG/l31KlPenbqUHfFwIoPDl/PLM0rIe9FLxlU X-Received: by 2002:a62:74b:: with SMTP id b72-v6mr1827433pfd.133.1527242119984; Fri, 25 May 2018 02:55:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527242119; cv=none; d=google.com; s=arc-20160816; b=cNQZ53qjfQgXp4SbpAjXYhUT1lnksCI87EUvTmvjbzB6XKokr03WkzspYmUoiELIvM zxtBoiYPqLL1bOnf5TbB2C1i1scen63L1+1E+68IDsyipjE7BjZMGhtahXwVxxcIh1zw H8ur+5lQjXY93c7geHr5Q3VpeYPjCpHldX7J1vT9lGOeilTaHxlFEm+5meGqIWOZGt3U Apu1hn5kHcYyFz0ZJzkfF/DLMfxZZTODGESvWZPSL55uNlnAwYIYndC+sjDFsp2dZf9g tj3QQ2KgRg3jdPqiRGokSX1CgLNwdl0DfVp9vUU/ajUchxqfENRptkZ/UdAkZavKjpJb eRuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=VAWc6TICGyf3KDrYClxpRyt3rMTjhlCyGr14Qf6nD8U=; b=Rp06Md8jONYx0GCh4H1dr9F/K1kmieOCOUYg5Ar2UDyQ5g0iKBgD+hsITLM5jgOPNB 6ShHAt8YjKeJNcXTiTnMnupQWywyZTh1UbNYgQIJlPy1ysVZOw1QRfZYztmrW3QSGVxV gdptadU88XhNL9Xfz/MtUOgxL3MEV7gcrhszJaWcsiGULuWyRWhAaTzG04+DWeM88SL6 JNL3wHr3MPnzS+bzsttjfslBrZlsxKYBtyNtxIg6emvw2aU+/JCtye57cYgDJuTVxZh4 tomXgm4WBvVasYWZ0Hr3u2z6Yra+9T60n78+bc3ZzsK0/I/FCgOMWCQeyGoRXWaiVtZW geKg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a92-v6si23667116pla.291.2018.05.25.02.55.05; Fri, 25 May 2018 02:55:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965758AbeEYJxB (ORCPT + 99 others); Fri, 25 May 2018 05:53:01 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:57632 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966133AbeEYJur (ORCPT ); Fri, 25 May 2018 05:50:47 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 213DF1688; Fri, 25 May 2018 02:50:47 -0700 (PDT) Received: from e112298-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 203CB3F25D; Fri, 25 May 2018 02:50:44 -0700 (PDT) From: Julien Thierry To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, mark.rutland@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Thierry Subject: [PATCH v4 21/26] arm64: Add build option for IRQ masking via priority Date: Fri, 25 May 2018 10:49:27 +0100 Message-Id: <1527241772-48007-22-git-send-email-julien.thierry@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527241772-48007-1-git-send-email-julien.thierry@arm.com> References: <1527241772-48007-1-git-send-email-julien.thierry@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Provide a build option to enable using GICv3 priorities to enable/disable interrupts. Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/Kconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index eb2cf49..ab214b9 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -938,6 +938,21 @@ config HARDEN_EL2_VECTORS If unsure, say Y. +config USE_ICC_SYSREGS_FOR_IRQFLAGS + bool "Use ICC system registers for IRQ masking" + select CONFIG_ARM_GIC_V3 + help + Using the ICC system registers for IRQ masking makes it possible + to simulate NMI on ARM64 systems. This allows several interesting + features (especially debug features) to be used on these systems. + + Say Y here to implement IRQ masking using ICC system + registers when the GIC System Registers are available. The changes + are applied dynamically using the alternatives system so it is safe + to enable this option on systems with older interrupt controllers. + + If unsure, say N + menuconfig ARMV8_DEPRECATED bool "Emulate deprecated/obsolete ARMv8 instructions" depends on COMPAT -- 1.9.1