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[209.132.180.67]) by mx.google.com with ESMTP id h8-v6si23543401pfi.115.2018.05.25.02.56.07; Fri, 25 May 2018 02:56:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966178AbeEYJyB (ORCPT + 99 others); Fri, 25 May 2018 05:54:01 -0400 Received: from foss.arm.com ([217.140.101.70]:57564 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966119AbeEYJue (ORCPT ); Fri, 25 May 2018 05:50:34 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A19A11AED; Fri, 25 May 2018 02:50:34 -0700 (PDT) Received: from e112298-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A0ACF3F25D; Fri, 25 May 2018 02:50:32 -0700 (PDT) From: Julien Thierry To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, mark.rutland@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Thierry Subject: [PATCH v4 16/26] arm64: daifflags: Include PMR in daifflags restore operations Date: Fri, 25 May 2018 10:49:22 +0100 Message-Id: <1527241772-48007-17-git-send-email-julien.thierry@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527241772-48007-1-git-send-email-julien.thierry@arm.com> References: <1527241772-48007-1-git-send-email-julien.thierry@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The addition of PMR should not bypass the semantics of daifflags. When DA_F are set, I bit is also set as no interrupts (even of higher priority) is allowed. When DA_F are cleared, I bit is cleared and interrupt enabling/disabling goes through ICC_PMR_EL1. Signed-off-by: Julien Thierry Cc: Catalin Marinas Cc: Will Deacon Cc: James Morse --- arch/arm64/include/asm/daifflags.h | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/daifflags.h b/arch/arm64/include/asm/daifflags.h index 8d91f22..3ae8139 100644 --- a/arch/arm64/include/asm/daifflags.h +++ b/arch/arm64/include/asm/daifflags.h @@ -18,8 +18,17 @@ #include -#define DAIF_PROCCTX 0 -#define DAIF_PROCCTX_NOIRQ PSR_I_BIT +#include + +#define DAIF_PROCCTX \ + (gic_prio_masking_enabled() ? \ + MAKE_ARCH_FLAGS(0, ICC_PMR_EL1_UNMASKED) : \ + 0) + +#define DAIF_PROCCTX_NOIRQ \ + (gic_prio_masking_enabled() ? \ + MAKE_ARCH_FLAGS(0, ICC_PMR_EL1_MASKED) : \ + PSR_I_BIT) /* mask/save/unmask/restore all exceptions, including interrupts. */ static inline void local_daif_mask(void) @@ -51,6 +60,10 @@ static inline void local_daif_unmask(void) : : : "memory"); + + /* Unmask IRQs in PMR if needed */ + if (gic_prio_masking_enabled()) + arch_local_irq_enable(); } static inline void local_daif_restore(unsigned long flags) -- 1.9.1