Received: by 2002:ac0:a594:0:0:0:0:0 with SMTP id m20-v6csp3317035imm; Fri, 25 May 2018 03:42:39 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo0nHZ9XyAZ/Yd2pZB6/9k76sU3aXjMY36hFgl91SBh/OuPyOhh7T5bVOLrkDFiqzrUlMuL X-Received: by 2002:a17:902:7244:: with SMTP id c4-v6mr676620pll.265.1527244959287; Fri, 25 May 2018 03:42:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527244959; cv=none; d=google.com; s=arc-20160816; b=A/XTwYYIN5ySPVfnYHl0+o6AbKpLUCtabsscLDNa0u5eX/70AXZaNMQzTSIqW4iIi0 VENGhP8HJSHR1BH3jmTLz30Z6z4P/iMvtIX9sOwPqJFd/H7VjuWaLPjHugFfTWGwIE70 LQFbM+rsW2BSoNjyszzUTQBeorfHqR9Oaf9e2R9JJzbKXQEgojC7kZ0WYXmtb3nzwYZz tspLx6Pa9KAyeGXplfeAZearBb01ihHXZYIzDuFr8Bpjm3/cazVuHMziA5IUa/pf54eS YOX/YnDL/y/XluW1THSh12O5CytQZgAIQ+02P7NSoIOnv004f0wCWZCzBMCxk8NYwUtu 2npQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject:arc-authentication-results; bh=QfD8Mr46DQKSLShh0FVwmKNySIOJx+iTtE1EDBTt99A=; b=owhONefj86VNpXZI68DOm32et4g1gKUmImD0nfeC3sPycBkEBjuiQOZys6EEbA8hFc yxoyHaPDT+Dgas8aTT+Q4JehBOVKnJLu1WXWu/5qNtYsNrEHL7cWCsMeHuVOS7JdpA68 uw8y8+NpxP1411496Qi9WUXIC1OwTQ5gURKyhYG2Y6O11rZsPvdsgFJmxvpkaGiSKzU1 gEFVfFoVZpM1WR1hcIu7kZ3IFdwstcR3ZlQtcaevN8LRDN9q723Wa4wZJemjpKeI3wNS Nx9Glkw8BYTMA10EjpsNaBd6fLMYTYNyJOOXiyFZaBe4lZ+Wv4eL1IygHZGCwrtTqyZy g6pA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x10-v6si22789616plv.1.2018.05.25.03.42.24; Fri, 25 May 2018 03:42:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966101AbeEYKl4 (ORCPT + 99 others); Fri, 25 May 2018 06:41:56 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:59298 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965255AbeEYKlz (ORCPT ); Fri, 25 May 2018 06:41:55 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F12E980D; Fri, 25 May 2018 03:41:54 -0700 (PDT) Received: from [10.1.206.73] (en101.cambridge.arm.com [10.1.206.73]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F0A873F578; Fri, 25 May 2018 03:41:52 -0700 (PDT) Subject: Re: [PATCH v4 02/26] arm64: cpufeature: Add cpufeature for IRQ priority masking To: Julien Thierry , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, mark.rutland@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com References: <1527241772-48007-1-git-send-email-julien.thierry@arm.com> <1527241772-48007-3-git-send-email-julien.thierry@arm.com> <54ff6127-928d-99a3-a6e9-59799628ca87@arm.com> From: Suzuki K Poulose Message-ID: <3f0afa54-8e98-798e-68dc-bbbc74bd9e19@arm.com> Date: Fri, 25 May 2018 11:41:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <54ff6127-928d-99a3-a6e9-59799628ca87@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/05/18 11:39, Julien Thierry wrote: > > > On 25/05/18 11:36, Suzuki K Poulose wrote: >> On 25/05/18 11:17, Julien Thierry wrote: >>> >>> >>> On 25/05/18 11:04, Suzuki K Poulose wrote: >>>> On 25/05/18 10:49, Julien Thierry wrote: >>>>> Add a cpufeature indicating whether a cpu supports masking interrupts >>>>> by priority. >>>> >>>> How is this different from the SYSREG_GIC_CPUIF cap ? Is it just >>>> the description ? >>> >>> More or less. >>> >>> It is just to have an easier condition in the rest of the series. Basically the PRIO masking feature is enabled if we have a GICv3 CPUIF working *and* the option was selected at build time. Before this meant that I was checking for the GIC_CPUIF cap inside #ifdefs (and putting alternatives depending on that inside #ifdefs as well). >>> >>> Having this as a separate feature feels easier to manage in the code. It also makes it clearer at boot time that the kernel will be using irq priorities (although I admit it was not the initial intention): >>> >>> [    0.000000] CPU features: detected: IRQ priority masking >>> >>> >>> But yes that new feature will be detected only if SYSREG_GIC_CPUIF gets detected as well. >> >> Well, you could always wrap the check like : >> >> static inline bool system_has_irq_priority_masking(void) >> { >>      return (IS_ENABLED(CONFIG_YOUR_CONFIG) && cpus_have_const_cap(HWCAP_SYSREG_GIC_CPUIF)); >> } >> >> and use it everywhere. >> > > Yes, but I can't use that in the asm parts that use alternatives and would need to surround them in #ifdef... :\ I thought there is _ALTERNATIVE_CFG() to base the alternative depend on a CONFIG_xxx ? Doesn't that solve the problem ? Suzuki