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[209.132.180.67]) by mx.google.com with ESMTP id e4-v6si23132796pln.331.2018.05.25.05.23.12; Fri, 25 May 2018 05:23:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=mXlXD6IR; dkim=pass header.i=@codeaurora.org header.s=default header.b=I8RSRwSY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966959AbeEYMW0 (ORCPT + 99 others); Fri, 25 May 2018 08:22:26 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:47888 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966601AbeEYMWW (ORCPT ); Fri, 25 May 2018 08:22:22 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7A44160F71; Fri, 25 May 2018 12:22:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527250941; bh=5VKLB8LCKVZTiUwTi5warGSkX8pjJaEP8FvfRykWyjw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mXlXD6IRGrAcrOoAGT8FwBvbhU9+0puPWyPJ9nney17DVa9m/+gr/X36T8eNVfMiR mz8HLMDtdw539Ene/RJe4cgcnXfWqXApWUZv0YMRVV3p9HntN+v9xBAmSeSJF7+6IO yvEblAMOmE+B7Z0clyJW7z9aKL7c7rhHh1AOC4Rs= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from absahu-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: absahu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D8BAC60C66; Fri, 25 May 2018 12:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527250940; bh=5VKLB8LCKVZTiUwTi5warGSkX8pjJaEP8FvfRykWyjw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I8RSRwSY/I0sCeZXiNx5n6vRzKeihhkCWLlMHFIMjCm+pGC5N85VAfau/EiwpPGs3 uYU1xlV9Q7skLKNqoiNLQp2iEz++JfwGuSMfVBiCm60+Cj6REAfij+lvx/sy7m7iwa TfGZFi2q5zhaSulfgpbt4roABEP6sfSgd82k+Scc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D8BAC60C66 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: Boris Brezillon Cc: David Woodhouse , Brian Norris , Marek Vasut , Richard Weinberger , Cyrille Pitchen , Miquel Raynal , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Andy Gross , Archit Taneja , Abhishek Sahu Subject: [PATCH v3 05/16] mtd: rawnand: qcom: remove dt property nand-ecc-step-size Date: Fri, 25 May 2018 17:51:33 +0530 Message-Id: <1527250904-21988-6-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527250904-21988-1-git-send-email-absahu@codeaurora.org> References: <1527250904-21988-1-git-send-email-absahu@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org QCOM NAND controller supports only one step size (512) so nand-ecc-step-size DT property is redundant. This property can be removed and ecc step size can be assigned with 512 value. Signed-off-by: Abhishek Sahu --- * Changes from v2: NEW CHANGE 1. Removed the custom logic and used the helper fuction. drivers/mtd/nand/raw/qcom_nandc.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index b554fb6..b538390 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2325,15 +2325,8 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host) bool wide_bus; int ecc_mode = 1; - /* - * the controller requires each step consists of 512 bytes of data. - * bail out if DT has populated a wrong step size. - */ - if (ecc->size != NANDC_STEP_SIZE) { - dev_err(nandc->dev, "invalid ecc size\n"); - return -EINVAL; - } - + /* controller only supports 512 bytes of data in each step */ + ecc->size = NANDC_STEP_SIZE; wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false; if (ecc->strength >= 8) { -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation