Received: by 2002:ac0:a594:0:0:0:0:0 with SMTP id m20-v6csp3623614imm; Fri, 25 May 2018 08:46:55 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpw5glWg2WPdd6re0uco0n3NcfjIAC5x+B6jxXS/w4Pm7wKSLwBtW+V52YSCyMXM6UzghIY X-Received: by 2002:a62:990f:: with SMTP id d15-v6mr3089652pfe.115.1527263215746; Fri, 25 May 2018 08:46:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527263215; cv=none; d=google.com; s=arc-20160816; b=tq7BgJashSziKDiPAu/HS0OIGUZqErVSi+CGSRQr8U32ooWlOLe0ArIVg/H34uqBZm h++B6MAXXjJ0/VIoTV81kh7SHzMkANODl1cmcRT6tR1cgmo5oiU+Jt0JtFF+Mhb9sGVD 4HRfLsnIbyHX+AKlGR9CtiXSaQ16pRO3Zew+3QfnHdxWoQvkNGKJorZjKqXZ18OIhHV2 Nt50VSGGbINLM1Ra/0WTwf95YEtYMISq/66ik++gzJ4rqIHJ8LT7kbyhxqLrgKCFCr3J n5j8rp/py7/QAN05stDfISeRJGDrQ3bOnvWuKfmRIINKFE3oZd3J0ebxco4YYGBUhcb+ xLxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date:arc-authentication-results; bh=6w48HAmc/WvNecHQCuLpvtVeAy23uDhr4tIBAm7WW7A=; b=rqaH8mYIexKuLRzmDngr776sMGBcdJTCRGizSCFnUJyeR/b62XAu6+oodTRpS8LHRz Xuoyt3sXcjxjOUqfXIp8RddHbm9eoTdaijhsO4qC+Gg1VgjD+i1lJ0GzPUadySnlzG6F Cxtrsuccxwa5mroiSxOl23wXXcKlJTIjEVviFq9pHU6LuEQv6YOprNVbruqDsuyElszL NyRgjB8CCyF6iSn9AvRz8CLhz6cttLlyauJQbNQhkQ+N5HJVuZrR7iEQYpCkEtFt6ANR krFrvx61bzBpy4Af8TXE5OBY0IYvCq+uGLhzS1QyQ+zYhGvKImyvWI9vx5zcWjYNBUeJ fgVA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.co.uk Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q4-v6si23487477plb.312.2018.05.25.08.46.41; Fri, 25 May 2018 08:46:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.co.uk Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966729AbeEYPp4 (ORCPT + 99 others); Fri, 25 May 2018 11:45:56 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:34450 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966128AbeEYPpy (ORCPT ); Fri, 25 May 2018 11:45:54 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sre) with ESMTPSA id 3B8722727AB Date: Fri, 25 May 2018 17:45:49 +0200 From: Sebastian Reichel To: Shawn Guo Cc: Sascha Hauer , Fabio Estevam , Will Deacon , Mark Rutland , Russell King , Ian Ray , Nandor Han , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: Re: [PATCHv4 1/2] ARM: imx53: add secure-reg-access support for PMU Message-ID: <20180525154549.r7gwxegcu4colhvs@earth.universe> References: <20180212123945.15732-1-sebastian.reichel@collabora.co.uk> <20180212123945.15732-2-sebastian.reichel@collabora.co.uk> <20180224074543.GF3217@dragon> <20180226134741.neqkpge33zo3pfzt@earth.universe> <20180227011033.GV3217@dragon> <20180227101712.3zwobvs4ox4jchcj@earth.universe> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="igqoj6vbus4t7g7w" Content-Disposition: inline In-Reply-To: <20180227101712.3zwobvs4ox4jchcj@earth.universe> User-Agent: NeoMutt/20180323 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --igqoj6vbus4t7g7w Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Shawn, On Tue, Feb 27, 2018 at 11:17:12AM +0100, Sebastian Reichel wrote: > Hi, >=20 > On Tue, Feb 27, 2018 at 09:10:34AM +0800, Shawn Guo wrote: > > On Mon, Feb 26, 2018 at 02:47:41PM +0100, Sebastian Reichel wrote: > > > On Sat, Feb 24, 2018 at 03:45:44PM +0800, Shawn Guo wrote: > > > > On Mon, Feb 12, 2018 at 01:39:44PM +0100, Sebastian Reichel wrote: > > > > > On i.MX53 it is necessary to set the DBG_EN bit in the > > > > > platform GPC register to enable access to PMU counters > > > > > other than the cycle counter. > > > > >=20 > > > > > Signed-off-by: Sebastian Reichel > > > > > --- > > > > > arch/arm/mach-imx/mach-imx53.c | 39 ++++++++++++++++++++++++++++= ++++++++++- > > > > > 1 file changed, 38 insertions(+), 1 deletion(-) > > > > >=20 > > > > > diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/m= ach-imx53.c > > > > > index 07c2e8dca494..658e28604dca 100644 > > > > > --- a/arch/arm/mach-imx/mach-imx53.c > > > > > +++ b/arch/arm/mach-imx/mach-imx53.c > > > > > @@ -28,10 +28,47 @@ static void __init imx53_init_early(void) > > > > > mxc_set_cpu_type(MXC_CPU_MX53); > > > > > } > > > > > =20 > > > > > +#define MXC_CORTEXA8_PLAT_GPC 0x63fa0004 > > > >=20 > > > > The base address should be retrieved from device tree. > > >=20 > > > DT has no entry for 0x63fa0000-0x63fa3fff. iMX53 TRM lists it as "ARM= Platform" > > > with 8 platform specific 32 bit registers. Do you think it's worth th= e trouble > > > adding a new binding? Do you have a suggestion for a compatible value? > >=20 > > Looking at it more closely, I feel that patching every single platform > > which needs to set up additional register for secure-reg-access support > > doesn't really scale. Can we have pmu driver do it with a phandle in > > DT pointing to the register and bit that need to be configured? >=20 > The PMU driver used to have a feature for initialising platform > specific bits, but it is currently being removed to make the PMU > code more maintainable. My understanding is, that it's very uncommon > to require platform specific setup to get secure-reg-access working. > E.g. it is not needed for newer iMX platforms. You never replied to this one. Are you fine with adding the function? This is kind of a deadlock situation with neither you wanting to enable the platform bit, nor the generic PMU driver. -- Sebastian --igqoj6vbus4t7g7w Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAlsIL6sACgkQ2O7X88g7 +prqNA/+NPBc0PDqbq8rrhPRw8MqT3/N+HrtlEHZ/GOs1XBWHpaEveQC6fHC2e06 zeyRjSoX7RVwQpkXNRprW51357GUWAO/w9XAsjgZwmchEd/47GLjMjJG4x3HHLd+ uVmwHNH06YnQMnVx0WIkLr6EKMDrUsfqm0Y2Bg49HS6pX6AwHPSMnjALc4368ejd wTXtghus1npyRcMqB/AK1uDEOzvyQNywzjy2OEKezV6y+zu7qVm7pPDzQcJRz/cx GoxOOI9bwv6MWgU9eWrufwRnfQ/XA7JM/Hnf7hj2a/+ojqnutcFnHpYvJqZoCBce CCLjAe8Hn+NQHSZIBcfHIXjkeb/D16u/Mk3NDzTr7UcQM6orK3jcX2Bz1N89ibS5 GdL+uLYXTcwfBcjD+g+fHKZj1wM8aVHrZ32uQu8CrClbcG/FNoRz9ZiUIPZYiL6q 7W4HVq1FyaGbjyUFxclXEZXFOr0YSgTqCRTJ237kbh2ZrLBX6JzlaOzvgeu0c6Or FcbGR8nHXkHd5dDIj/UDiIHCf33i1CcWf0OyoihN/m38xCn9LuQXBq4gkCsp1p+p tJktTqVh4DobEqVV+urtu5CZBfeS4lVFnBcdhL3c+r5NAemx8cAy4rzKvbdCAqHj P9Z9vcktXYJpT5shVlxYDB6hBxgdaqrNDJwwWcyA5NLt2DMnaf4= =L6n4 -----END PGP SIGNATURE----- --igqoj6vbus4t7g7w--