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[209.132.180.67]) by mx.google.com with ESMTP id r7-v6si1422533pgq.675.2018.05.27.07.18.48; Sun, 27 May 2018 07:19:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032634AbeE0OSk convert rfc822-to-8bit (ORCPT + 99 others); Sun, 27 May 2018 10:18:40 -0400 Received: from mail.bootlin.com ([62.4.15.54]:51034 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965011AbeE0OSi (ORCPT ); Sun, 27 May 2018 10:18:38 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id AB6092071D; Sun, 27 May 2018 16:18:36 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from xps13 (unknown [37.169.232.104]) by mail.bootlin.com (Postfix) with ESMTPSA id DF08420376; Sun, 27 May 2018 16:18:34 +0200 (CEST) Date: Sun, 27 May 2018 16:18:32 +0200 From: Miquel Raynal To: Stefan Agner Cc: Boris Brezillon , Benjamin Lindqvist , dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, thierry.reding@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, Lucas Stach , richard@nod.at, marcel@ziswiler.com, krzk@kernel.org, digetx@gmail.com, jonathanh@nvidia.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, Mirza Krak , linux-mtd@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver Message-ID: <20180527161832.1152be6e@xps13> In-Reply-To: <146a3abbbff4dcef30ad662a0fb85ff1@agner.ch> References: <86fdf19ec92b732709732fb60199f16488b4b727.1526990589.git.stefan@agner.ch> <20180524135335.6aa0b7a4@bbrezillon> <146a3abbbff4dcef30ad662a0fb85ff1@agner.ch> Organization: Bootlin X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stefan, On Thu, 24 May 2018 14:19:18 +0200, Stefan Agner wrote: > On 24.05.2018 13:53, Boris Brezillon wrote: > > Hi Benjamin, > > > > On Thu, 24 May 2018 13:30:14 +0200 > > Benjamin Lindqvist wrote: > > > >> Hi Stefan, > >> > >> It seems to me that a probe similar to what the BootROM does shouldn't > >> be awfully complicated to implement - just cycle through the switch > >> cases in case of an ECC error. But I guess that's more of an idea for > >> further improvements rather than a comment to the patch set under > >> review. > > > > Nope, not really an option, because you're not guaranteed that the NAND > > will be used as a boot media, and the first page or first set of pages > > might just be erased. > > > > Yeah I did not meant probing like the Boot ROM does. > > What I meant was using only the ECC modes which are supported by the > Boot ROM when the driver tries to choose a viable mode. So that would > be: > - RS t=4 > - BCH t=8 > - BCH t=16 > > Maybe we could add a property to enable that behavior: > > tegra,use-bootable-ecc-only; I'm not sure a property is needed. As there is currently no official user of this driver, why not turning mandatory the nand-ecc-xxx properties? In the documentation you can add a note saying that using other algorithms than the three above is not supported by the BootROM. > > >> > >> However, I think that allowing for an override of the oobsize > >> inference would be a good idea before merging, no? This could just be > >> a trivial #ifdef (at least temporarily). If you agree but don't feel > >> like doing it yourself, I'd be happy to pitch in. Let me know. > > > > That's why we have nand-ecc-xxx properties in the DT. > > > > Yes, nand-ecc-strength is the first thing I plan to implement, that way > strength can be defined in dt. > > -- > Stefan Thanks, Miquèl