Received: by 2002:ac0:a5b6:0:0:0:0:0 with SMTP id m51-v6csp1886292imm; Sun, 27 May 2018 19:27:27 -0700 (PDT) X-Google-Smtp-Source: AB8JxZp3giGaFtXiQ/JiUWWYVDJdZia5Nl/X67AXjOAeCeMufVuR5tNXgd4xu2Yjzy9YuqVhFlu0 X-Received: by 2002:a17:902:10c:: with SMTP id 12-v6mr11811533plb.252.1527474447775; Sun, 27 May 2018 19:27:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527474447; cv=none; d=google.com; s=arc-20160816; b=pJNlK4gcsReXdWI9QHtbYY17aLdFmh4gDg10qbdFTvd/38Kjserfu6XBvNw6oEpTnn t6cDmmzW3AgxgWAIbHeROljrtGh9waFvxp19W9jIZXRY4fkBnDEmmJAbicR8/2NHEwSr BRMZSMmQ8Hz1kAsbXudZ8fYBmhTSB8y7B7bm0bGNn90e1J4GuQ/oyerPRsCeemTDQZrF H7s+c2Om/s3LwOi8y2bdiTkf1dmASHAX/hqRJZd2+JtYzdF1FKoFD1djCYXOTrFqhRHQ pW6T6br/8Wk9Bj7X/BE2JbOWb8WqknyaPuoockijWb+XtkI2s6W6/WjEiVE3YexORpsJ sVhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date:dkim-signature:arc-authentication-results; bh=67EmKBpppMKbSxMYb7S1bOj70U5Eb7enHm8c61VGfvA=; b=qP8RGJxknTnFm3YD9OBLZ3tizh7yP1gJBdakfr2fGph5KVaNhzSGQJRfXl2a7bZFKi Ml14n6wCb3w82MunUEbKc6PXjGZfb+IBtwZw3Zp4Ps+dyksAVcOc5Vx/Nyj2WVpWuHsG wf9BLtE/nnDjhM+BfsqZL/4O/VZv7mWxEhYT/HO90z7gCjWe5l2B19iNIq6NdxjGTtQm ui52ISF4UIuh0D+eIKB0fegUSBVzQunhntDnVMKGH50XCXndGKJgZoWBp1DC60l4hBUM bRoHcj2fdOrX824dExYVlAFy1NyeoKSd4S8W9/HxjwGhdgWd1ZgxmuCXoyNiLI669ndV MDpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=G7Nbtpkt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g33-v6si30332453plb.297.2018.05.27.19.27.12; Sun, 27 May 2018 19:27:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=G7Nbtpkt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752994AbeE1C1E (ORCPT + 99 others); Sun, 27 May 2018 22:27:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:44586 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752970AbeE1C1C (ORCPT ); Sun, 27 May 2018 22:27:02 -0400 Received: from dragon (unknown [104.237.91.108]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2A5372086D; Mon, 28 May 2018 02:26:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1527474421; bh=WslBHHhOx38+E+oUw2HLU7FJz3QfS/fWZip6C92AMSE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=G7Nbtpkt2aBx8ExBTltdH4HBgBdyMrieAOksUOn7F8sD1AQ4iHHDO7U8UA+jQq8O/ BDFWbTt1VO4gv9tPw7EfwlWSdLzaWA9EZov/7e4qkqE+TBzQ+2ec3FcvEnguF8nqcM U1tApxExK39wCWq929a21kjNftogEATYyqTL+JOw= Date: Mon, 28 May 2018 10:26:54 +0800 From: Shawn Guo To: Sebastian Reichel Cc: Sascha Hauer , Fabio Estevam , Will Deacon , Mark Rutland , Russell King , Ian Ray , Nandor Han , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: Re: [PATCHv4 1/2] ARM: imx53: add secure-reg-access support for PMU Message-ID: <20180528022652.GA3143@dragon> References: <20180212123945.15732-1-sebastian.reichel@collabora.co.uk> <20180212123945.15732-2-sebastian.reichel@collabora.co.uk> <20180224074543.GF3217@dragon> <20180226134741.neqkpge33zo3pfzt@earth.universe> <20180227011033.GV3217@dragon> <20180227101712.3zwobvs4ox4jchcj@earth.universe> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180227101712.3zwobvs4ox4jchcj@earth.universe> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Feb 27, 2018 at 11:17:12AM +0100, Sebastian Reichel wrote: > Hi, > > On Tue, Feb 27, 2018 at 09:10:34AM +0800, Shawn Guo wrote: > > On Mon, Feb 26, 2018 at 02:47:41PM +0100, Sebastian Reichel wrote: > > > On Sat, Feb 24, 2018 at 03:45:44PM +0800, Shawn Guo wrote: > > > > On Mon, Feb 12, 2018 at 01:39:44PM +0100, Sebastian Reichel wrote: > > > > > On i.MX53 it is necessary to set the DBG_EN bit in the > > > > > platform GPC register to enable access to PMU counters > > > > > other than the cycle counter. > > > > > > > > > > Signed-off-by: Sebastian Reichel > > > > > --- > > > > > arch/arm/mach-imx/mach-imx53.c | 39 ++++++++++++++++++++++++++++++++++++++- > > > > > 1 file changed, 38 insertions(+), 1 deletion(-) > > > > > > > > > > diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c > > > > > index 07c2e8dca494..658e28604dca 100644 > > > > > --- a/arch/arm/mach-imx/mach-imx53.c > > > > > +++ b/arch/arm/mach-imx/mach-imx53.c > > > > > @@ -28,10 +28,47 @@ static void __init imx53_init_early(void) > > > > > mxc_set_cpu_type(MXC_CPU_MX53); > > > > > } > > > > > > > > > > +#define MXC_CORTEXA8_PLAT_GPC 0x63fa0004 > > > > > > > > The base address should be retrieved from device tree. > > > > > > DT has no entry for 0x63fa0000-0x63fa3fff. iMX53 TRM lists it as "ARM Platform" > > > with 8 platform specific 32 bit registers. Do you think it's worth the trouble > > > adding a new binding? Do you have a suggestion for a compatible value? > > > > Looking at it more closely, I feel that patching every single platform > > which needs to set up additional register for secure-reg-access support > > doesn't really scale. Can we have pmu driver do it with a phandle in > > DT pointing to the register and bit that need to be configured? > > The PMU driver used to have a feature for initialising platform > specific bits, but it is currently being removed to make the PMU > code more maintainable. My understanding is, that it's very uncommon > to require platform specific setup to get secure-reg-access working. > I.e. it is not needed for newer iMX platforms. Are you saying this is a very specific setup required by i.MX53 only? In that case, I can live with it. Shawn