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[209.132.180.67]) by mx.google.com with ESMTP id j123-v6si30849952pfd.207.2018.05.27.22.57.33; Sun, 27 May 2018 22:57:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=W6+K8kTc; dkim=pass header.i=@codeaurora.org header.s=default header.b=IL67CH4Q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753327AbeE1F4A (ORCPT + 99 others); Mon, 28 May 2018 01:56:00 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56578 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752527AbeE1Fz5 (ORCPT ); Mon, 28 May 2018 01:55:57 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B5600601D7; Mon, 28 May 2018 05:55:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527486956; bh=Cxyk/P/5b/lOfZPru2oEYdr+bqKYPDTG8fcFTAY7zOU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=W6+K8kTcqias6xHqsO24L2I49XjecDsM+uNBWpRR2wsRrHO6qHwH7f6sagXMBxLji 4Sy7+iD8pTuZmrGBw9K4kqrn1xkH+USqQ/aiB92QE9M/nteblDP3oxdxetZy0oclpJ HLmf8Mo7KfTk6r480/K7lGNCEulDA5OYgU7UDr3Y= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id CA479601D7; Mon, 28 May 2018 05:55:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527486954; bh=Cxyk/P/5b/lOfZPru2oEYdr+bqKYPDTG8fcFTAY7zOU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=IL67CH4Q4gTs7r9MI3qxjar07ijNmrmzR5IH+VdPUacjrpVkU7zQlH3BnT0XAy1Le YCzjQk35GybAGvDwQ/2ZMABOKGtMNYbjEkon4J/7nZTgPlASxLgYvhk4YAA8Rb99CH /uxHk+/vKpNjkQfGPgcV1qq6ZnPQPNzSz/2Rob1w= MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 28 May 2018 11:25:54 +0530 From: Abhishek Sahu To: Miquel Raynal Cc: Boris Brezillon , David Woodhouse , Brian Norris , Marek Vasut , Richard Weinberger , Cyrille Pitchen , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Andy Gross , Archit Taneja Subject: Re: [PATCH v3 05/16] mtd: rawnand: qcom: remove dt property nand-ecc-step-size In-Reply-To: <20180526104259.210d96fc@xps13> References: <1527250904-21988-1-git-send-email-absahu@codeaurora.org> <1527250904-21988-6-git-send-email-absahu@codeaurora.org> <20180526104259.210d96fc@xps13> Message-ID: <4b3a6c3b975f58ea68b7f0749b5fcd54@codeaurora.org> X-Sender: absahu@codeaurora.org User-Agent: Roundcube Webmail/1.2.5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2018-05-26 14:12, Miquel Raynal wrote: > Hi Abhishek, > > On Fri, 25 May 2018 17:51:33 +0530, Abhishek Sahu > wrote: > >> QCOM NAND controller supports only one step size (512) so >> nand-ecc-step-size DT property is redundant. This property >> can be removed and ecc step size can be assigned with 512 value. >> >> Signed-off-by: Abhishek Sahu >> --- >> * Changes from v2: >> >> NEW CHANGE >> >> 1. Removed the custom logic and used the helper fuction. >> drivers/mtd/nand/raw/qcom_nandc.c | 11 ++--------- >> 1 file changed, 2 insertions(+), 9 deletions(-) >> >> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c >> b/drivers/mtd/nand/raw/qcom_nandc.c >> index b554fb6..b538390 100644 >> --- a/drivers/mtd/nand/raw/qcom_nandc.c >> +++ b/drivers/mtd/nand/raw/qcom_nandc.c >> @@ -2325,15 +2325,8 @@ static int qcom_nand_host_setup(struct >> qcom_nand_host *host) >> bool wide_bus; >> int ecc_mode = 1; >> >> - /* >> - * the controller requires each step consists of 512 bytes of data. >> - * bail out if DT has populated a wrong step size. >> - */ >> - if (ecc->size != NANDC_STEP_SIZE) { >> - dev_err(nandc->dev, "invalid ecc size\n"); >> - return -EINVAL; >> - } >> - >> + /* controller only supports 512 bytes of data in each step */ > > "512 bytes data steps" > Thanks Miquel. Will update that. Regards, Abhishek >> + ecc->size = NANDC_STEP_SIZE; >> wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false; >> >> if (ecc->strength >= 8) { > > Once corrected: > > Acked-by: Miquel Raynal