Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S262129AbTICNaX (ORCPT ); Wed, 3 Sep 2003 09:30:23 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S262147AbTICNaX (ORCPT ); Wed, 3 Sep 2003 09:30:23 -0400 Received: from mail.jlokier.co.uk ([81.29.64.88]:54411 "EHLO mail.jlokier.co.uk") by vger.kernel.org with ESMTP id S262129AbTICNaV (ORCPT ); Wed, 3 Sep 2003 09:30:21 -0400 Date: Wed, 3 Sep 2003 14:29:32 +0100 From: Jamie Lokier To: Geert Uytterhoeven Cc: Roman Zippel , Kars de Jong , Linux/m68k kernel mailing list , Linux Kernel Development Subject: Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this Message-ID: <20030903132932.GA21530@mail.jlokier.co.uk> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.1i Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 674 Lines: 17 Geert Uytterhoeven wrote: > > BTW the 020/030 caches are VIVT (and also only writethrough), the 040/060 > > caches are PIPT. > > That explains a bit. But the '060 stores are coherent, while the '040 stores > aren't. The L1 cache is coherent on the '040 according to the results. It's the store buffer snooping which fails. Presumably the CPU core is looking ahead at recent writes comparing just virtual addresses. -- Jamie - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/