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[209.132.180.67]) by mx.google.com with ESMTP id z14-v6si24921936pgc.617.2018.05.29.00.41.28; Tue, 29 May 2018 00:41:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FQ+uPQk4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755036AbeE2HkE (ORCPT + 99 others); Tue, 29 May 2018 03:40:04 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:44833 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754902AbeE2HkB (ORCPT ); Tue, 29 May 2018 03:40:01 -0400 Received: by mail-wr0-f195.google.com with SMTP id y15-v6so23718098wrg.11 for ; Tue, 29 May 2018 00:40:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=spUcHuGGRFfom5Bvxc7fiV4lEIZW7RkGpmr6jItjG/0=; b=FQ+uPQk4MYXTtGQEvculCLTA1sHP1hs8cnRcST6QeNHt3iCBCOmsGmVJCqeYxQboIW 3nDMHz6GOwxPPiHoJ9evBFi70LqYrspAa9GtUpF1ptZoOgmEpx16uXu08ONHJYQK0QCD 81NB96+zvAnAVHSA484VucFwOJ9J2GSybNpyo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=spUcHuGGRFfom5Bvxc7fiV4lEIZW7RkGpmr6jItjG/0=; b=Ltemlif3Lf2BrEb3S3gNc1bH82WDLAOuM6ZJd2G9mUvRe3N9HeC5xP5b3x+cvr9huC 6J70rtY5SYDJdd9yByUdZLd3+ZDsOmU+nu4rK9dNrhV/BgYH2RqzKcUru7HBOp3acZH5 xToqNXGUBoirnZAeyEWL23yMPmCnItm4bUDK6g3TDtB1mmsYc61faLyC16HV8Sc6uFaQ Wf0kGn1oIlT4Af7Vb+otnq0Ap4v4yCP9KOmnm3z1izfUdOhpYJDtkx8j93c66ZiURpuA tKYyD9zOw2ioi9XsJ87Uxq5PsY81J24KClVTL1E1s/HdgsmGZWe5Ko8lTG0p07nrN6Q5 Ia/w== X-Gm-Message-State: ALKqPwejuEcxTc9uqLUabUDIsZy6Mt8kMojSYECwzbaC8u+bN9FDl/je HkFlXBfPA3BFmSKv2PMs6J1vMA== X-Received: by 2002:adf:dc8b:: with SMTP id r11-v6mr11241187wrj.263.1527579600533; Tue, 29 May 2018 00:40:00 -0700 (PDT) Received: from dell ([2.27.167.23]) by smtp.gmail.com with ESMTPSA id x73-v6sm11588992wmf.21.2018.05.29.00.39.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 May 2018 00:39:59 -0700 (PDT) Date: Tue, 29 May 2018 08:39:58 +0100 From: Lee Jones To: Matti Vaittinen Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, lgirdwood@gmail.com, broonie@kernel.org, mazziesaccount@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mikko.mutanen@fi.rohmeurope.com, heikki.haikola@fi.rohmeurope.com Subject: Re: [PATCH v2 0/6] mfd/regulator/clk: bd71837: ROHM BD71837 PMIC driver Message-ID: <20180529073958.GB4790@dell> References: <20180528090003.GA8778@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20180528090003.GA8778@localhost.localdomain> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 28 May 2018, Matti Vaittinen wrote: > Patch series adding support for ROHM BD71837 PMIC. > > BD71837 is a programmable Power Management IC for powering single-core, > dual-core, and quad-core SoC’s such as NXP-i.MX 8M. It is optimized for > low BOM cost and compact solution footprint. It integrates 8 buck > regulators and 7 LDO’s to provide all the power rails required by the > SoC and the commonly used peripherals. > > The driver aims to not limit the usage of PMIC. Thus the buck and LDO > naming is generic and not tied to any specific purposes. However there > is following limitations which make it mostly suitable for use cases > where the processor where PMIC driver is running is powered by the PMIC: > > - The PMIC is not re-initialized if it resets. PMIC may reset as a > result of voltage monitoring (over/under voltage) or due to reset > request. Driver is only initializing PMIC at probe. This is not > problem as long as processor controlling PMIC is powered by PMIC. > > - The PMIC internal state machine is ignored by driver. Driver assumes > the PMIC is wired so that it is always in "run" state when controlled > by the driver. FYI, this patch-set is going to be difficult to manage since it was not sent 'threaded'. As people start replying to different patches, they are going to scatter-bomb throughout all of the recipient's inboxes. If/when you send a subsequent version, could you please ensure you send the set threaded so the patches keep in relation to one another as they are reviewed? -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog