Received: by 2002:ac0:a5b6:0:0:0:0:0 with SMTP id m51-v6csp3533571imm; Tue, 29 May 2018 08:50:49 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpePQ/lY+MlW1nZNi7ClZ0JO7UQ9orwghfOI13mNXNcifE+EdKmNIOvGsCrWktzqZIDSDCd X-Received: by 2002:aa7:81cc:: with SMTP id c12-v6mr18060978pfn.169.1527609049766; Tue, 29 May 2018 08:50:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527609049; cv=none; d=google.com; s=arc-20160816; b=e7JkbjZRDEw3ffGU7l9rmWDt7ZOdypGztwzMpYmqVSXObNSTzBDRLIeeZctM9T+6Xg E998yYqMhZX4xmGOoZFP8NKF0GFisWTV0hqaorclvg7WWPZE3jtbzY+O5L1ABdlzDVFC c3Ljefvm4vBf1xuqYul5yyw2+QY/cOKOvfAEp5jbk5TQR5/zy4y+bk/9JoNb8X8D3HSO frhJBPwBWu/jqUo89PkZg/Vj640NddeRK7Rseh/0cqiZWmIZIQoaojb3nVxlExN3lzfx Z6wyyv5VxMbv4GMAaopPRmsxAn38XuYiQ6cc+oGO/gNJWBskcUmmdyMCr4oKMTQ7hhTn WiTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=ZMtIERzmKxoW9t+L0vmDQtE8tYg2BmT8DeW+qmHPkD4=; b=MrPdNWf+a2kDNrmiypLQk8mU60eUITPwIwvDsXz+469AxDqyhWvmzUHGBClCoCAWu0 nbZ9Qfk89BRS2FBN5VavG+vmIEsnmyN243tENYHqK1yvm9GX2+gDFLcl8knjD+gIdmLX rSzMcVQD61kvfp0dL/Prt0dM1/RhnZ5ybhetj5Bx2sGwgQNOJIrAx2i2eJ73PLzm7xPq 2F0rxoiYA9gO9pmfUhmpPooqG9+PTW4mhopsPkN4OQkFMp6PeojSUdJR3ns2J7ip5W3k kLOOZHMqgI+Qk+uyJIXtbJeTu2sNYNujY60j3f0YSz5GTweG45JW14qyvk3566fRLE77 KMvg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v4-v6si31684035pfe.306.2018.05.29.08.50.35; Tue, 29 May 2018 08:50:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936939AbeE2Psl (ORCPT + 99 others); Tue, 29 May 2018 11:48:41 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:43376 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936450AbeE2PoG (ORCPT ); Tue, 29 May 2018 11:44:06 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3353815AD; Tue, 29 May 2018 08:44:06 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 490203F25D; Tue, 29 May 2018 08:44:05 -0700 (PDT) From: Mark Rutland To: linux-kernel@vger.kernel.org Cc: Mark Rutland , Boqun Feng , Will Deacon Subject: [PATCHv2 02/16] atomics/treewide: remove redundant atomic_inc_not_zero() definitions Date: Tue, 29 May 2018 16:43:32 +0100 Message-Id: <20180529154346.3168-3-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180529154346.3168-1-mark.rutland@arm.com> References: <20180529154346.3168-1-mark.rutland@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When atomic_inc_not_zero(v) isn't defined, will define it as falling back to atomic_add_unless((v), 1, 0), so there's no need for arch code to do so. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Acked-by: Peter Zijlstra (Intel) Cc: Boqun Feng Cc: Will Deacon --- arch/arc/include/asm/atomic.h | 2 -- arch/hexagon/include/asm/atomic.h | 2 -- arch/riscv/include/asm/atomic.h | 9 --------- 3 files changed, 13 deletions(-) diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h index 67121b5ff3a3..cecdf3403caf 100644 --- a/arch/arc/include/asm/atomic.h +++ b/arch/arc/include/asm/atomic.h @@ -336,8 +336,6 @@ ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3) c; \ }) -#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) - #define atomic_inc(v) atomic_add(1, v) #define atomic_dec(v) atomic_sub(1, v) diff --git a/arch/hexagon/include/asm/atomic.h b/arch/hexagon/include/asm/atomic.h index 287aa9f394f3..d2feeba93c44 100644 --- a/arch/hexagon/include/asm/atomic.h +++ b/arch/hexagon/include/asm/atomic.h @@ -197,8 +197,6 @@ static inline int atomic_fetch_add_unless(atomic_t *v, int a, int u) return __oldval; } -#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) - #define atomic_inc(v) atomic_add(1, (v)) #define atomic_dec(v) atomic_sub(1, (v)) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 739e810c857e..0e27e050ba14 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -375,15 +375,6 @@ static __always_inline int atomic64_add_unless(atomic64_t *v, long a, long u) } #endif -/* - * The extra atomic operations that are constructed from one of the core - * LR/SC-based operations above. - */ -static __always_inline int atomic_inc_not_zero(atomic_t *v) -{ - return atomic_fetch_add_unless(v, 1, 0); -} - #ifndef CONFIG_GENERIC_ATOMIC64 static __always_inline long atomic64_inc_not_zero(atomic64_t *v) { -- 2.11.0