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From:   Wanpeng Li <kernellwp@gmail.com>
Date:   Wed, 30 May 2018 08:46:11 +0800
Message-ID: <CANRm+Cw0umo1DTR0wohYb0EpvTRWOoEuUCyrWcif9_-WG1we=Q@mail.gmail.com>
Subject: Re: [PATCH] KVM: VMX: Optimize tscdeadline timer latency
To:     Paolo Bonzini <pbonzini@redhat.com>
Cc:     Radim Krcmar <rkrcmar@redhat.com>,
        LKML <linux-kernel@vger.kernel.org>, kvm <kvm@vger.kernel.org>
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On Wed, 30 May 2018 at 01:08, Paolo Bonzini <pbonzini@redhat.com> wrote:

> On 29/05/2018 16:31, Radim Kr=C4=8Dm=C3=A1=C5=99 wrote:
> > 2018-05-29 16:23+0200, Radim Kr=C4=8Dm=C3=A1=C5=99:
> >> 2018-05-29 14:53+0800, Wanpeng Li:
> >>> From: Wanpeng Li <wanpengli@tencent.com>
> >>>
> >>> 'Commit d0659d946be0 ("KVM: x86: add option to advance tscdeadline
> >>> hrtimer expiration")' advances the tscdeadline (the timer is emulated
> >>> by hrtimer) expiration in order that the latency which is incurred
> >>> by hypervisor (apic_timer_fn -> vmentry) can be avoided. This patch
> >>> adds the advance tscdeadline expiration support to which the
tscdeadline
> >>> timer is emulated by VMX preemption timer to reduce the hypervisor
> >>> lantency (handle_preemption_timer -> vmentry). clockevents
infrastruture
> >>> can program minimum delay if hrtimer feeds a expiration in the past,
> >>> we set delta_tsc to 1(which will be converted to 0 before vmentry)
> >>> which can lead to an immediately vmexit when delta_tsc is not bigger
> >>> than advance ns.
> >>>
> >>> This patch can reduce ~63% latency (~4450 cycles to ~1660 cycles on
> >>> a haswell desktop) for kvm-unit-tests/tscdeadline_latency when testin=
g
> >>> busy waits.
> >>>
> >>> Cc: Paolo Bonzini <pbonzini@redhat.com>
> >>> Cc: Radim Kr=C4=8Dm=C3=A1=C5=99 <rkrcmar@redhat.com>
> >>> Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
> >>> ---
> >>> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> >>> @@ -12444,6 +12444,12 @@ static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu, u64 guest_deadline_tsc)
> >>>     tscl =3D rdtsc();
> >>>     guest_tscl =3D kvm_read_l1_tsc(vcpu, tscl);
> >>>     delta_tsc =3D max(guest_deadline_tsc, guest_tscl) - guest_tscl;
> >>> +   lapic_timer_advance_cycles =3D nsec_to_cycles(vcpu,
lapic_timer_advance_ns);
> >>> +   if (delta_tsc > lapic_timer_advance_cycles)
> >>> +           delta_tsc -=3D lapic_timer_advance_cycles;
> >>> +   else
> >>> +           delta_tsc =3D 1;
> >>
> >> Why don't we just "return 1" to say that the timer has expired?
> >
> > This case might be rare, so setting delta_tsc =3D 0 would be safer.

> Queued with this change.  Indeed this case matches vmx_arm_hv_timer so
> it's preferrable.

Agreed, thanks.

Regards,
Wanpeng Li