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[209.132.180.67]) by mx.google.com with ESMTP id d4-v6si35333251plr.373.2018.05.30.19.06.13; Wed, 30 May 2018 19:06:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932637AbeEaCFo (ORCPT + 99 others); Wed, 30 May 2018 22:05:44 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:27759 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932588AbeEaCFn (ORCPT ); Wed, 30 May 2018 22:05:43 -0400 X-UUID: 99528c128264462f9bcd11a99a18eebe-20180531 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1901706697; Thu, 31 May 2018 10:05:38 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 31 May 2018 10:05:36 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 31 May 2018 10:05:36 +0800 Message-ID: <1527732336.9842.3.camel@mtkswgap22> Subject: Re: [PATCH] PCI: mediatek: Add system pm support for MT2712 From: Ryder Lee To: CC: , , , , , , , , , , , , , , , , Date: Thu, 31 May 2018 10:05:36 +0800 In-Reply-To: <1527647736-19986-1-git-send-email-honghui.zhang@mediatek.com> References: <1527647736-19986-1-git-send-email-honghui.zhang@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2018-05-30 at 10:35 +0800, honghui.zhang@mediatek.com wrote: > From: Honghui Zhang > > The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all > the internel control register will be reset after system resume. The PCIe > link should be re-established and the related control register values should > be re-set after system resume. > > Signed-off-by: Honghui Zhang > CC: Ryder Lee > --- > drivers/pci/host/pcie-mediatek.c | 82 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 82 insertions(+) > > diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c > index dabf1086..60f98d92 100644 > --- a/drivers/pci/host/pcie-mediatek.c > +++ b/drivers/pci/host/pcie-mediatek.c > @@ -132,12 +132,14 @@ struct mtk_pcie_port; > /** > * struct mtk_pcie_soc - differentiate between host generations > * @need_fix_class_id: whether this host's class ID needed to be fixed or not > + * @pm_support: whether the host's MTCMOS will be off when suspend > * @ops: pointer to configuration access functions > * @startup: pointer to controller setting functions > * @setup_irq: pointer to initialize IRQ functions > */ > struct mtk_pcie_soc { > bool need_fix_class_id; > + bool pm_support; > struct pci_ops *ops; > int (*startup)(struct mtk_pcie_port *port); > int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); > @@ -1179,12 +1181,91 @@ static int mtk_pcie_probe(struct platform_device *pdev) > return err; > } > > +static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev) > +{ > + struct platform_device *pdev; > + struct mtk_pcie *pcie; > + struct mtk_pcie_port *port; > + const struct mtk_pcie_soc *soc; > + > + pdev = to_platform_device(dev); > + pcie = platform_get_drvdata(pdev); How about this - struct mtk_pcie *pcie = dev_get_drvdata(dev); > + soc = pcie->soc; > + if (!soc->pm_support) > + return 0; > + > + list_for_each_entry(port, &pcie->ports, list) { > + clk_disable_unprepare(port->ahb_ck); > + clk_disable_unprepare(port->sys_ck); > + phy_power_off(port->phy); > + } > + > + return 0; > +} > + > +static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev) > +{ > + struct platform_device *pdev; > + struct mtk_pcie *pcie; > + struct mtk_pcie_port *port; > + const struct mtk_pcie_soc *soc; > + int ret; > + > + pdev = to_platform_device(dev); > + pcie = platform_get_drvdata(pdev); struct mtk_pcie *pcie = dev_get_drvdata(dev); > + soc = pcie->soc; > + if (!soc->pm_support) > + return 0; > + > + list_for_each_entry(port, &pcie->ports, list) { > + ret = phy_power_on(port->phy); > + if (ret) { > + dev_err(dev, "could not power on phy\n"); > + return ret; > + } > + ret = clk_prepare_enable(port->sys_ck); > + if (ret) { > + dev_err(dev, "enable sys clock error\n"); > + phy_power_off(port->phy); > + return ret; > + } > + > + ret = clk_prepare_enable(port->ahb_ck); > + if (ret) { > + dev_err(dev, "enable ahb clock error\n"); > + phy_power_off(port->phy); > + clk_disable_unprepare(port->sys_ck); > + return ret; > + } > + > + ret = soc->startup(port); > + if (ret) { > + dev_err(dev, "pcie linkup failed\n"); > + phy_power_off(port->phy); > + clk_disable_unprepare(port->sys_ck); > + clk_disable_unprepare(port->ahb_ck); > + return ret; > + } > + > + if (IS_ENABLED(CONFIG_PCI_MSI)) > + mtk_pcie_enable_msi(port); > + } > + > + return 0; > +} > +