Received: by 2002:ac0:a5b6:0:0:0:0:0 with SMTP id m51-v6csp160984imm; Wed, 30 May 2018 20:30:25 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJ0BX7g59IWr0LAx5DeRLyvoxdt5m9n3McN1n7UPLp0oeZ/oTke7+Hcdl9bPER4C4dRvoaC X-Received: by 2002:a17:902:284b:: with SMTP id e69-v6mr5174008plb.240.1527737425629; Wed, 30 May 2018 20:30:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527737425; cv=none; d=google.com; s=arc-20160816; b=Qe9PQuQre4ZKHtrJp0kO1rapszRwwpETwbVbUpA/jxtm9pDceSByuOJ/FE7kvh+x0t Udem0UaNXYafUzjW5uy4irxKIRZbB4BVS6xhZoie9t8+memtkXJruXPJuPu5dgdotG7g YrygKgzENtHlWsPWVWzZTF6BmJx8ZMIZwwK4PFNDjOh6RL+QfGlUaXCNEmieqXfZEr/W LYIb6fEc2lIqbbNl7PPQpjprCE9egC4kSS8Yar7pddwyWJkvT/dvKmPoF5r36qwpQ6tv zvOkaNMrXavVII8kidab1z7TEEPrXyCQbJKofaIpZBcJjVOe7KMPkWfAaGgd35GFJsgm UI+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=Ocx9mhAxwFclN3KquczbqN5wdIFj8rfmL2TywgYaRGk=; b=lCb0d+Ci+xsqVS9jXv/RJrn84HS6B9OpWLPrXh1k3va5I4HUs+ZWcAH+UZbe1OACsN fE35c2rRagUPGf9W3TOnEDoFMOd/h8x1WPVHWVs/dZNqRMclpuhatoYoouLqIJVtDHmb xHuCuK1TGpSVQgyUvwyd5Q5PzD5uzMC+zUEaIsLX6pNyzOqXIypJ3NbtTPYebY3g79nJ YHjGUGhyOhWuWwZiuDZ4RvWCBQPKkCyKH/CGzhdCszfnS/YtE3HLDY7GxsOqDEBYXMEH WIiCo5sYMmV6Md+5AdhdGlH6Qbfzt+R2j+Ln7rWGO5xCcbrN552tde9JTH24nDOkbF/i HslQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 38-v6si36872782plc.446.2018.05.30.20.30.12; Wed, 30 May 2018 20:30:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932799AbeEaD3P (ORCPT + 99 others); Wed, 30 May 2018 23:29:15 -0400 Received: from ZXSHCAS1.zhaoxin.com ([203.148.12.81]:39883 "EHLO ZXSHCAS1.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932637AbeEaD3N (ORCPT ); Wed, 30 May 2018 23:29:13 -0400 Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Thu, 31 May 2018 11:29:03 +0800 Received: from timguo-System-Product-Name.zhaoxin.com (10.29.8.54) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Thu, 31 May 2018 11:29:01 +0800 From: David Wang To: , , , , , , , , CC: , , , , , , David Wang Subject: [PATCH] x86/mce: add CMCI support for Centaur CPUs Date: Thu, 31 May 2018 11:28:58 +0800 Message-ID: <1527737338-4036-1-git-send-email-davidwang@zhaoxin.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.29.8.54] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To zxbjmbx3.zhaoxin.com (10.29.252.165) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Newer Centaur support CMCI mechanism, which is compatible with INTEL CMCI. Signed-off-by: David Wang --- arch/x86/Kconfig | 12 ++++++++++++ arch/x86/kernel/cpu/mcheck/mce.c | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index dda87a3..1adff5f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1130,6 +1130,18 @@ config X86_MCE_AMD Additional support for AMD specific MCE features such as the DRAM Error Threshold. +config X86_MCE_CENTAUR + def_bool y + prompt "CENTAUR MCE features" + depends on CPU_SUP_CENTAUR && X86_MCE_INTEL + help + Additional support for Centaur specific MCE features such as + MCE broadcasting and CMCI support. + New Centaur CPU support MCE broadcasting. + New Centaur CPU support CMCI which is fully compliant with Intel CMCI. + + If unsure, say N here. + config X86_ANCIENT_MCE bool "Support for old Pentium 5 / WinChip machine checks" depends on X86_32 && X86_MCE diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index cd76380..2ebafc7 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1727,6 +1727,7 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) } } +#ifdef CONFIG_X86_MCE_CENTAUR static void mce_centaur_feature_init(struct cpuinfo_x86 *c) { struct mca_config *cfg = &mca_cfg; @@ -1740,7 +1741,12 @@ static void mce_centaur_feature_init(struct cpuinfo_x86 *c) if (cfg->monarch_timeout < 0) cfg->monarch_timeout = USEC_PER_SEC; } + mce_intel_feature_init(c); + mce_adjust_timer = cmci_intel_adjust_timer; } +#else +static inline void mce_centaur_feature_init(struct cpuinfo_x86 *c) { } +#endif static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) { -- 1.9.1