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[209.132.180.67]) by mx.google.com with ESMTP id v61-v6si36892195plb.499.2018.05.30.22.52.17; Wed, 30 May 2018 22:52:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753881AbeEaFvK (ORCPT + 99 others); Thu, 31 May 2018 01:51:10 -0400 Received: from mga11.intel.com ([192.55.52.93]:55268 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751037AbeEaFvF (ORCPT ); Thu, 31 May 2018 01:51:05 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 May 2018 22:51:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,462,1520924400"; d="scan'208";a="233383198" Received: from helong-vb.png.intel.com ([10.226.242.245]) by fmsmga006.fm.intel.com with ESMTP; 30 May 2018 22:51:00 -0700 From: "Hean-Loong, Ong" To: Rob Herring , Dinh Nguyen , Daniel Vetter , Laurent Pinchart Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, hean.loong.ong@intel.com, yves.vandervennet@intel.com, chin.liang.see@intel.com, Ong@vger.kernel.org Subject: [PATCHv<8> 0/3] Intel FPGA Video and Image Processing Suite Date: Thu, 31 May 2018 13:50:48 +0800 Message-Id: <1527745851-3339-1-git-send-email-hean.loong.ong@intel.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ong, Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the FPGA FrameBuffer 2. The piece of hardware in discussion is the SoC FPGA where Linux runs on the ARM chip and the FGPA is driven by its NIOS soft core with its own proprietary firmware. For example the application from the ARM Linux would have to write information on the /dev/fb0 with the information stored in the SDRAM to be fetched by the FPGA framebuffer IP and displayed on the Display Port Monitor. Ong Hean Loong (3): ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite ARM:drm ivip Intel FPGA Video and Image Processing Suite .../devicetree/bindings/display/altr,vip-fb2.txt | 112 +++++++++++ arch/arm/configs/socfpga_defconfig | 5 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/ivip/Kconfig | 14 ++ drivers/gpu/drm/ivip/Makefile | 9 + drivers/gpu/drm/ivip/intel_vip_conn.c | 96 ++++++++++ drivers/gpu/drm/ivip/intel_vip_core.c | 162 ++++++++++++++++ drivers/gpu/drm/ivip/intel_vip_drv.h | 52 ++++++ drivers/gpu/drm/ivip/intel_vip_of.c | 193 ++++++++++++++++++++ 10 files changed, 646 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt create mode 100644 drivers/gpu/drm/ivip/Kconfig create mode 100644 drivers/gpu/drm/ivip/Makefile create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c create mode 100644 drivers/gpu/drm/ivip/intel_vip_core.c create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h create mode 100644 drivers/gpu/drm/ivip/intel_vip_of.c