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[209.132.180.67]) by mx.google.com with ESMTP id q2-v6si36491210plh.136.2018.05.31.00.18.48; Thu, 31 May 2018 00:19:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=KZsNEwmN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754010AbeEaHRY (ORCPT + 99 others); Thu, 31 May 2018 03:17:24 -0400 Received: from mail-lf0-f68.google.com ([209.85.215.68]:42647 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753825AbeEaHRW (ORCPT ); Thu, 31 May 2018 03:17:22 -0400 Received: by mail-lf0-f68.google.com with SMTP id v135-v6so8170188lfa.9; Thu, 31 May 2018 00:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:date:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=IJd+8US5KdLW0ucBAUkT8mf3jqagiMl5veZ/eC6j78g=; b=KZsNEwmNihABqBABBkAeuUeiqFwuynOW8E4acLxaaV53XIOy7b7ue90FkPi/BBTWnp Rh3ZlldJDtUCOaSc35vYGAB+mBVWZyQGMtRVW50ybfKrFXJ0HpL+QMYoKg2g5KRoS7Gs pKlLXV+9vUzrpGYrjA6T/qYGIo4KdJKwbQNIBJ8bGudxv3aeaDS/I7IJDyB9UlkCyujJ cyqQeEdkrY5dVhSbRxErkwv9qCLcuggqqqkLm95wYhZFk8ZvcVWKbmlVCnh2ExfCfjpR txq8ktLGchWgen6FN//5VTaFPnNpKixXbIxKTt9WGUh4OaEZ7mZU7R5fHFt4JRgKmHEd mfFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:date:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=IJd+8US5KdLW0ucBAUkT8mf3jqagiMl5veZ/eC6j78g=; b=A9gsSc6XXkkDEE/+4ejhc+h+DdbEYkIgHC5yMYdFviE0ss79u31E4ETr8Tu2TSNoJx dVhS73hOOLLBJMe3wejmpaAjeCEL8QzPGHW04p+Js3lelJB+UmYnHS1HokTU7SEwr1df 0DjjlDOdBwxpYbW9WBLbdGGYPxksV7f9lLt1mLBogfKnmO4Ko/ZJQZUkhxiEHPRJDV0n RhKlGhDF/eVrzcVV0eaICfS0OJAaX9omYrlPV4MtQtc1UPOf09s/qgQrQ6HkLxgZqQFa 0aBWw8QKplbdoODXguDDWt9SwkAkVaWorm+N2Z2443HIO1jnDHC65LpXu5TxQqJpyLbs 2hsA== X-Gm-Message-State: ALKqPwcCPUeAI8pW0UNLy53DfIOVYS72ovDCyjETjZLwbwXGXjPo7q7k NyCVWU13dQFY5Slp2ks9bGY= X-Received: by 2002:a19:16e1:: with SMTP id 94-v6mr3265478lfw.45.1527751040463; Thu, 31 May 2018 00:17:20 -0700 (PDT) Received: from localhost.localdomain ([213.255.186.34]) by smtp.gmail.com with ESMTPSA id k12-v6sm1494413lje.94.2018.05.31.00.17.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 31 May 2018 00:17:19 -0700 (PDT) From: Matti Vaittinen X-Google-Original-From: Matti Vaittinen Date: Thu, 31 May 2018 10:17:17 +0300 To: Rob Herring Cc: Matti Vaittinen , mturquette@baylibre.com, sboyd@kernel.org, mark.rutland@arm.com, lee.jones@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, mazziesaccount@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mikko.mutanen@fi.rohmeurope.com, heikki.haikola@fi.rohmeurope.com Subject: Re: [PATCH v4 2/6] mfd: bd71837: Devicetree bindings for ROHM BD71837 PMIC Message-ID: <20180531071717.GG13528@localhost.localdomain> References: <3b05ca98a671a762013c312f8b70543402ee7556.1527669443.git.matti.vaittinen@fi.rohmeurope.com> <20180531030129.GA16122@rob-hp-laptop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180531030129.GA16122@rob-hp-laptop> User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Rob, Thanks for the review! On Wed, May 30, 2018 at 10:01:29PM -0500, Rob Herring wrote: > On Wed, May 30, 2018 at 11:42:03AM +0300, Matti Vaittinen wrote: > > Document devicetree bindings for ROHM BD71837 PMIC MFD. > > + - interrupts : The interrupt line the device is connected to. > > + - interrupt-controller : Marks the device node as an interrupt controller. > > What sub blocks have interrupts? The PMIC can generate interrupts from events which cause it to reset. Eg, irq from watchdog line change, power button pushes, reset request via register interface etc. I don't know any generic handling for these interrupts. In "normal" use-case this PMIC is powering the processor where driver is running and I do not see reasonable handling because power-reset is going to follow the irq. This IRQ might be relevant if use for PMIC is such that it is not powering the processor where the driver is runninng. Then the controlling processor can get the notification that chips powered by PMIC are resetting. But handling for this must be use-case specific, right? So in short - none of the current sub-devices use the IRQs - they are there for specific use-cases which some boards may implement. Any suggestions how to document the available interrupts? (power button line, sw reset etc). My current assumption has been that one who is interested in using these irqs should really also see the data-sheet for IRQs. But I admit that documenting available interrupts here would be helpful. I will just cook up some explanation and send it as a patch if no suggestions on how to document those. Patches 3/6 and 6/6 from the series were already applied to Mark's tree. So how should I send further patches? Should I still send the whole series (including already applied patches 3/6 and 6/6) or only the ones I change? > > +Example: > > + > > + pmic: bd71837@4b { > > Node names should be generic ideally. So "pmic@4b" I'll change that. > > + clk: bd71837-32k-out { > > clock-controller { And I'll change that too. > > > + compatible = "rohm,bd71837-clk"; > > + #clock-cells = <0>; > > + clock-frequency = <32768>; > > Can this be anything else? Not so that I know. Frequency is fixed. Is there a problem with this? Br, Matti Vaittinen