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[209.132.180.67]) by mx.google.com with ESMTP id l1-v6si4126371plt.389.2018.05.31.03.14.02; Thu, 31 May 2018 03:14:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UrJeL3hY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754371AbeEaKNd (ORCPT + 99 others); Thu, 31 May 2018 06:13:33 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:55128 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754207AbeEaKNa (ORCPT ); Thu, 31 May 2018 06:13:30 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w4VADDON027398; Thu, 31 May 2018 05:13:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1527761593; bh=UvyDF/MquVP+Vk0Sgm+hstpLRSskdV8ToMQ9Dov+vRM=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=UrJeL3hY/HRjviuM6rq+rHgTt0WPgJGQpcJkrKrBTMNbbn3Suu8W3h85svtldpIE7 xXCf+SW1U3j/bT4byKXraAbkRL8gLTS9C320zfSpMbEBiN9zhqluwS7a8T6C+XGzbH QeR6M0V+nAE3vez7Ge+3z/UhIMSSAu8ZLJ0Odchw= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4VADDxG022953; Thu, 31 May 2018 05:13:13 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 31 May 2018 05:13:13 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 31 May 2018 05:13:13 -0500 Received: from [172.24.190.215] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4VAD9xW004443; Thu, 31 May 2018 05:13:10 -0500 Subject: Re: [PATCH v2 3/6] clk: ti: dra7: Add clkctrl clock data for the mcan clocks To: Rob Herring CC: , , , , , , , , References: <20180530141133.3711-1-faiz_abbas@ti.com> <20180530141133.3711-4-faiz_abbas@ti.com> <20180531040350.GA25132@rob-hp-laptop> From: Faiz Abbas Message-ID: Date: Thu, 31 May 2018 15:44:43 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180531040350.GA25132@rob-hp-laptop> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thursday 31 May 2018 09:33 AM, Rob Herring wrote: > On Wed, May 30, 2018 at 07:41:30PM +0530, Faiz Abbas wrote: >> Add clkctrl data for the m_can clocks and register it within the ... >> >> diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h >> index 5e1061b15aed..d7549c57cac3 100644 >> --- a/include/dt-bindings/clock/dra7.h >> +++ b/include/dt-bindings/clock/dra7.h >> @@ -168,5 +168,6 @@ >> #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) >> #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) >> #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) >> +#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) > > ADC and mcan are the same thing? > The register to control MCAN clocks is called ADC_CLKCTRL, Yes. Thanks, Faiz