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[209.132.180.67]) by mx.google.com with ESMTP id w16-v6si10117768pgc.232.2018.05.31.03.17.31; Thu, 31 May 2018 03:17:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=cIsZDAOy; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754384AbeEaKRH (ORCPT + 99 others); Thu, 31 May 2018 06:17:07 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:41879 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754314AbeEaKRF (ORCPT ); Thu, 31 May 2018 06:17:05 -0400 Received: by mail-pl0-f67.google.com with SMTP id az12-v6so12971971plb.8; Thu, 31 May 2018 03:17:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Cqk5RdVr0b2Obodour61xFYSmA/ZqMwkA4CcsE1J0zg=; b=cIsZDAOyopDTK6LbXJD/GTpS7HDJ493SFFPDFfZ64WNklJrUjHquHxa3D+H5RrwgLN wt62uojVFvr7t6dtAf1D3V05418pH5jgAs4w2Xk71MSSGyZCxWHS/QROZ60MCnead8YZ PUalEddlf6qdCoYwqvU1Ek2LIrpeIdwKsCg4CJTpXM/bM/P9yCwQbSm3i2GkhRCrRezI /F91VwNvpRPWENnxk/xde9A7sWW7/9POOIt053Jkw2zaDmVuS71+oegXNbsimm6LeFov FfFmMZ5+XwBsHkhdTCsRmoxzE2bQFQ/AU7l3nL44N+/L/sDQjjOCYRyRH0oWcoTW3jcE giHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Cqk5RdVr0b2Obodour61xFYSmA/ZqMwkA4CcsE1J0zg=; b=OPq2lfb5Obj7LXXdJTo4lRazegoviRKkdeYpj3ZpSrP3yxHnxSJ4bxCG3XXSaJBjbs PC4HClPocuS2D8NA72wyz597vCJoViOCgGssJ3IHRWNSqeGYmI6Jch/wQQfJFDzIubqH BPTd6jogFNPezzeWRQoxz9CcqMuc4d8Q/BeuUSB7zVv4c6vR8rtWULot6czDJTrzeWTS 9imbpSqpUuUHbHr80IhFZTbFr5gnObuAIM1sS/Dt5KsXwNubkIomZ+olrPl/rT2INdzp AfEyiinRz5xyM4a9Yybod27PZ627rQvOzhy3Y5rXCjzxFraL7TJk+cIa6Rr4VTE+vDn+ SxsQ== X-Gm-Message-State: ALKqPweD2cvTSaufRf9v/Azcmuehtki5QREhiB98EVirRHP2Lbq6Vnr6 LDROhfs5lxT1Vb9Hl8OejGV9hG/8PD+SXRlu/38= X-Received: by 2002:a17:902:b417:: with SMTP id x23-v6mr6500030plr.388.1527761824355; Thu, 31 May 2018 03:17:04 -0700 (PDT) MIME-Version: 1.0 References: <1527154169-32380-1-git-send-email-michel.pollet@bp.renesas.com> <1527154169-32380-3-git-send-email-michel.pollet@bp.renesas.com> In-Reply-To: From: M P Date: Thu, 31 May 2018 11:16:53 +0100 Message-ID: Subject: Re: [PATCH v7 2/5] dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation To: Geert Uytterhoeven Cc: michel.pollet@bp.renesas.com, linux-renesas-soc@vger.kernel.org, Simon Horman , Phil Edworthy , buserror+upstream@gmail.com, Michael Turquette , sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, geert+renesas@glider.be, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Geert, On Fri, 25 May 2018 at 10:23, Geert Uytterhoeven wrote: > > Hi Michel, > > On Thu, May 24, 2018 at 11:28 AM, Michel Pollet > wrote: > > The Renesas R9A06G032 SYSCTRL node description. > > > > Signed-off-by: Michel Pollet > > Thanks for your patch! > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt > > @@ -0,0 +1,32 @@ > > +* Renesas R9A06G032 SYSCTRL > > + > > +Required Properties: > > + > > + - compatible: Must be: > > + - "renesas,r9a06g032-sysctrl" > > + - reg: Base address and length of the SYSCTRL IO block. > > + - #clock-cells: Must be 1 > > No clocks/clock-names for the external clock inputs? > > "RZ/N1 has 3 clock sources, 1 reference clock inputs for RGMII, and 2 > reference clock outputs for RMII/MII." > > Given the documentation explicitly mentions the module clocks are to be > used for power-management, you may want to add #power-domain-cells as well, > and let the driver register clock domain. But that can be added later > (although it will break backwards compatibility with old DTBs). > > As PWRCTRL_* registers allow to reset individual modules, #reset-cells is > another thing to add later. It's good to start thinking early about how to > reference resets, though. > E.g. on other Renesas-SoCs, module resets uses the same numerical > references as module clocks. As you said, could we add all that later, as appropriate? Here I tried to trim it down to the the bare minimum -- my previous version of the driver had separate reset descriptors, but this one has been all compacted to do just what it's supposed to do: clocks. Or, so you want to add another DT index to refer to other reset indexes etc? ie not use the of_clk_src_onecell_get provider? That COULD work and yes, the indexes would stay the same, I'd just have to get the reset descriptor from the clock object. We haven't had a use for individual resets so far. > Gr{oetje,eeting}s, > > Geert Cheers, Michel