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[209.132.180.67]) by mx.google.com with ESMTP id z141-v6si4013304pfc.95.2018.05.31.03.57.28; Thu, 31 May 2018 03:57:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kusF0yfY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754602AbeEaK4b (ORCPT + 99 others); Thu, 31 May 2018 06:56:31 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:16387 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754464AbeEaK43 (ORCPT ); Thu, 31 May 2018 06:56:29 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w4VAuKfw027256; Thu, 31 May 2018 05:56:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1527764180; bh=+ofvphIDuRl8OqoX+HandxGcUYUw5qsCIiukZUZT0DU=; h=Subject:To:References:CC:From:Date:In-Reply-To; b=kusF0yfYmEDXw2gbrVSyC1LDCyHh+P1ZtBZbfzY1sT8danb5c724iSGZdQLRVMbai qLOfyI3tjDw+IwS4+4KeNNC/VtRzYUip1CWYdiY3KVsCS/MmIPW1IIhVR5J3EWHQCN USnCqF+WMSbQpWukT1xWWgrCVcZnG/o44SEfMZSY= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4VAuKQX019327; Thu, 31 May 2018 05:56:20 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 31 May 2018 05:56:20 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 31 May 2018 05:56:19 -0500 Received: from [172.24.190.233] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4VAuFi3016564; Thu, 31 May 2018 05:56:16 -0500 Subject: Re: [PATCH v2 5/7] PCI: dwc: Add legacy interrupt callback handler To: Gustavo Pimentel , , , , , , References: CC: , , From: Kishon Vijay Abraham I Message-ID: <820a245a-77e9-b231-24df-7e7df7ea0c32@ti.com> Date: Thu, 31 May 2018 16:26:15 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday 17 May 2018 10:39 PM, Gustavo Pimentel wrote: > Add a legacy interrupt callback handler. Currently DesignWare IP don't > allow trigger legacy interrupts. > > Signed-off-by: Gustavo Pimentel Acked-by: Kishon Vijay Abraham I > --- > Change v1->v2: > - Nothing changed, just to follow the patch set version. > > drivers/pci/dwc/pcie-designware-ep.c | 10 ++++++++++ > drivers/pci/dwc/pcie-designware-plat.c | 3 +-- > drivers/pci/dwc/pcie-designware.h | 6 ++++++ > 3 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c > index a4baa0d..9822127 100644 > --- a/drivers/pci/dwc/pcie-designware-ep.c > +++ b/drivers/pci/dwc/pcie-designware-ep.c > @@ -370,6 +370,16 @@ static const struct pci_epc_ops epc_ops = { > .stop = dw_pcie_ep_stop, > }; > > +int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > + struct device *dev = pci->dev; > + > + dev_err(dev, "EP cannot trigger legacy IRQs\n"); > + > + return -EINVAL; > +} > + > int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > u8 interrupt_num) > { > diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c > index 654dcb5..90a8c95 100644 > --- a/drivers/pci/dwc/pcie-designware-plat.c > +++ b/drivers/pci/dwc/pcie-designware-plat.c > @@ -84,8 +84,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, > > switch (type) { > case PCI_EPC_IRQ_LEGACY: > - dev_err(pci->dev, "EP cannot trigger legacy IRQs\n"); > - return -EINVAL; > + return dw_pcie_ep_raise_legacy_irq(ep, func_no); > case PCI_EPC_IRQ_MSI: > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); > case PCI_EPC_IRQ_MSIX: > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h > index a0ab12f..69e6e17 100644 > --- a/drivers/pci/dwc/pcie-designware.h > +++ b/drivers/pci/dwc/pcie-designware.h > @@ -350,6 +350,7 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp) > void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); > int dw_pcie_ep_init(struct dw_pcie_ep *ep); > void dw_pcie_ep_exit(struct dw_pcie_ep *ep); > +int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no); > int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > u8 interrupt_num); > int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > @@ -369,6 +370,11 @@ static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) > { > } > > +static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) > +{ > + return 0; > +} > + > static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > u8 interrupt_num) > { >