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[209.132.180.67]) by mx.google.com with ESMTP id 87-v6si37692234pfo.137.2018.05.31.07.08.44; Thu, 31 May 2018 07:08:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=rGWy4t2z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755345AbeEaOHu (ORCPT + 99 others); Thu, 31 May 2018 10:07:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:37364 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755093AbeEaOHq (ORCPT ); Thu, 31 May 2018 10:07:46 -0400 Received: from mail-qk0-f174.google.com (mail-qk0-f174.google.com [209.85.220.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8FA10208B3; Thu, 31 May 2018 14:07:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1527775665; bh=CnFpJ4WF23W2Cc4CoHTGOiJfoy/bsF0MkKWA9uMjaQ4=; h=In-Reply-To:References:From:Date:Subject:To:Cc:From; b=rGWy4t2zWs6zTHIU14s7mypSl+hF3Si6wA4zOUB4CdJdo8eEKumlH+oKEQR0wkFnZ UcZc8sKP53zS4HXrBGfZsk85d56ARnqGRA6W5i9940qAvxXpNLHo5eoxabUOr4ylBz XtuwSdVEKnQqBAdB+zLU0/VWBwghJ+giyhPqJB7o= Received: by mail-qk0-f174.google.com with SMTP id d130-v6so11880768qkc.2; Thu, 31 May 2018 07:07:45 -0700 (PDT) X-Gm-Message-State: APt69E2N7XqEDxTMm6CnESvGzltluM+ezhGhZYeGsYGAVliq2cZcagO3 yHnTKKVx90QcHn9XQeqUNzkKMwZkjck6n7gMBQ== X-Received: by 2002:a37:6188:: with SMTP id v130-v6mr6632148qkb.43.1527775664712; Thu, 31 May 2018 07:07:44 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a0c:9b02:0:0:0:0:0 with HTTP; Thu, 31 May 2018 07:07:24 -0700 (PDT) In-Reply-To: <20180531102315.GA5150@localhost.localdomain> References: <3b05ca98a671a762013c312f8b70543402ee7556.1527669443.git.matti.vaittinen@fi.rohmeurope.com> <20180531030129.GA16122@rob-hp-laptop> <20180531071717.GG13528@localhost.localdomain> <20180531102315.GA5150@localhost.localdomain> From: Rob Herring Date: Thu, 31 May 2018 09:07:24 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 2/6] mfd: bd71837: Devicetree bindings for ROHM BD71837 PMIC To: Matti Vaittinen Cc: Matti Vaittinen , Michael Turquette , Stephen Boyd , Mark Rutland , Lee Jones , Liam Girdwood , Mark Brown , linux-clk , devicetree@vger.kernel.org, "linux-kernel@vger.kernel.org" , mikko.mutanen@fi.rohmeurope.com, heikki.haikola@fi.rohmeurope.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 31, 2018 at 5:23 AM, Matti Vaittinen wrote: > On Thu, May 31, 2018 at 10:17:17AM +0300, Matti Vaittinen wrote: >> Hello Rob, >> >> Thanks for the review! >> >> On Wed, May 30, 2018 at 10:01:29PM -0500, Rob Herring wrote: >> > On Wed, May 30, 2018 at 11:42:03AM +0300, Matti Vaittinen wrote: >> > > Document devicetree bindings for ROHM BD71837 PMIC MFD. >> > > + - interrupts : The interrupt line the device is connected to. >> > > + - interrupt-controller : Marks the device node as an interrupt controller. >> > >> > What sub blocks have interrupts? >> >> The PMIC can generate interrupts from events which cause it to reset. >> Eg, irq from watchdog line change, power button pushes, reset request >> via register interface etc. I don't know any generic handling for these >> interrupts. In "normal" use-case this PMIC is powering the processor >> where driver is running and I do not see reasonable handling because >> power-reset is going to follow the irq. >> > > Oh, but when reading this I understand that the interrupt-controller > property should at least be optional. I don't think it should. The h/w either has an interrupt controller or it doesn't. My concern is you added it but nothing uses it which tells me your binding is incomplete. I'd rather see complete bindings even if you don't have drivers. For example, as-is, there's not really any need for the clocks child node. You can just make the parent a clock provider. But we need a complete picture of the h/w to make that determination. Rob