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[209.132.180.67]) by mx.google.com with ESMTP id z18-v6si37010314pfd.357.2018.05.31.07.48.27; Thu, 31 May 2018 07:48:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=bqGQ7GEY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755430AbeEaOp3 (ORCPT + 99 others); Thu, 31 May 2018 10:45:29 -0400 Received: from mail.kernel.org ([198.145.29.99]:43020 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755117AbeEaOpY (ORCPT ); Thu, 31 May 2018 10:45:24 -0400 Received: from mail-qt0-f181.google.com (mail-qt0-f181.google.com [209.85.216.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5CB0A208B4; Thu, 31 May 2018 14:45:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1527777923; bh=m6m/kXEMN0SfpYHOKLdQL5l6jmw4djYBnQ8CuHFEqSc=; h=In-Reply-To:References:From:Date:Subject:To:Cc:From; b=bqGQ7GEYHqK0zzad/RzbewvA5DBEA9CPKRRkPqs5HNJjsNYcCJhTk93ZCW3e9pm9K 1CiU8ZH2W5yxm0ulKhm/6HiNtzuOA8NBs6XLf1qcnMscabMiL+lzeYOK+zFWKxzx1k kJ8Yu/Z33159c6N1iTDOHcgGq1gdipXBYIsflyqI= Received: by mail-qt0-f181.google.com with SMTP id h5-v6so20124118qtm.13; Thu, 31 May 2018 07:45:23 -0700 (PDT) X-Gm-Message-State: APt69E2VQMFsslpRXZlj+AiuxAg0Qio/dYXyEkga0gdXhrYZKSRRFn2M jfgp3zN4O+0yFO1oYtmaXV3SRNRaUOzqEAwVwA== X-Received: by 2002:ac8:1802:: with SMTP id q2-v6mr6458710qtj.22.1527777922493; Thu, 31 May 2018 07:45:22 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a0c:9b02:0:0:0:0:0 with HTTP; Thu, 31 May 2018 07:45:02 -0700 (PDT) In-Reply-To: <1527737273-8387-3-git-send-email-djw@t-chip.com.cn> References: <1527737273-8387-1-git-send-email-djw@t-chip.com.cn> <1527737273-8387-3-git-send-email-djw@t-chip.com.cn> From: Rob Herring Date: Thu, 31 May 2018 09:45:02 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 2/5] gpio: syscon: rockchip: add GPIO_MUTE support for rk3328 To: Levin Du Cc: "open list:ARM/Rockchip SoC..." , Wayne Chou , Heiko Stuebner , devicetree@vger.kernel.org, Linus Walleij , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" , Mark Rutland , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 30, 2018 at 10:27 PM, wrote: > From: Levin Du > > In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec > mute control, can also be used for general purpose. It is manipulated by > the GRF_SOC_CON10 register. > > Signed-off-by: Levin Du > > --- > > Changes in v3: > - Change from general gpio-syscon to specific rk3328-gpio-mute > > Changes in v2: > - Rename gpio_syscon10 to gpio_mute in doc > > Changes in v1: > - Refactured for general gpio-syscon usage for Rockchip SoCs. > - Add doc rockchip,gpio-syscon.txt > > .../bindings/gpio/rockchip,rk3328-gpio-mute.txt | 28 +++++++++++++++++++ > drivers/gpio/gpio-syscon.c | 31 ++++++++++++++++++++++ > 2 files changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt > > diff --git a/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt > new file mode 100644 > index 0000000..10bc632 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt > @@ -0,0 +1,28 @@ > +Rockchip RK3328 GPIO controller dedicated for the GPIO_MUTE pin. > + > +In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute > +control, can also be used for general purpose. It is manipulated by the > +GRF_SOC_CON10 register. > + > +Required properties: > +- compatible: Should contain "rockchip,rk3328-gpio-mute". > +- gpio-controller: Marks the device node as a gpio controller. > +- #gpio-cells: Should be 2. The first cell is the pin number and > + the second cell is used to specify the gpio polarity: > + 0 = Active high, > + 1 = Active low. > + > +Example: > + > + grf: syscon@ff100000 { > + compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; > + > + gpio_mute: gpio-mute { Node names should be generic: gpio { This also means you can't add another GPIO node in the future and you'll have to live with "rockchip,rk3328-gpio-mute" covering more than 1 GPIO if you do need to add more GPIOs. > + compatible = "rockchip,rk3328-gpio-mute"; > + gpio-controller; > + #gpio-cells = <2>; > + }; > + }; > + > +Note: The gpio_mute node should be declared as the child of the GRF (General > +Register File) node. The GPIO_MUTE pin is referred to as <&gpio_mute 0>. This is wrong because you should have 2 cells. The phandle doesn't count as a cell. Rob