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Subject: Re: [PATCH] PCI: Check for PCIe downtraining conditions
To:     "Alex G." <mr.nuke.me@gmail.com>, Alex_Gagniuc@Dellteam.com,
        bhelgaas@google.com
Cc:     Austin.Bolen@dell.com, Shyam.Iyer@dell.com, keith.busch@intel.com,
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From:   Sinan Kaya <okaya@codeaurora.org>
Message-ID: <32d58835-2f35-0b80-38d0-b9ff603619dd@codeaurora.org>
Date:   Thu, 31 May 2018 12:13:51 -0400
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On 5/31/2018 12:01 PM, Alex G. wrote:
>>       PCI: Add pcie_print_link_status() to log link speed and whether it's limited
> This one, I have, but it's not what I need. This looks at the available
> bandwidth from root port to endpoint, whereas I'm only interested in
> downtraining between endpoint and upstream port.

I see what you are saying. 

With a little bit of effort, you can reuse the same code.

Here is an attempt.

You can probably extend pcie_bandwidth_available() to put an optional parent bridge
device for your own use case and terminate the loop around here.

https://elixir.bootlin.com/linux/v4.17-rc7/source/drivers/pci/pci.c#L5182

Then, you can use the existing code to achieve what you are looking for via
pcie_print_link_status() by adding an optional parent parameter.

	bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
	bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width, *parent*);


If parent parameter is NULL, code can walk all the way to root as it is doing today.
If it is not, then will terminate the loop on the first iteration.

-- 
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.