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Subject: Re: [PATCH] PCI: Check for PCIe downtraining conditions
To:     Sinan Kaya <okaya@codeaurora.org>, Alex_Gagniuc@Dellteam.com,
        bhelgaas@google.com
Cc:     Austin.Bolen@dell.com, Shyam.Iyer@dell.com, keith.busch@intel.com,
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From:   "Alex G." <mr.nuke.me@gmail.com>
Message-ID: <954892f0-196d-b11c-c2a0-e4a0e4be4b8c@gmail.com>
Date:   Thu, 31 May 2018 12:27:20 -0500
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On 05/31/2018 12:11 PM, Sinan Kaya wrote:
> On 5/31/2018 12:49 PM, Alex G. wrote:
>>> 	bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
>>> 	bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width, *parent*);
>> That's confusing. I'd expect _capable() and _available() to be
>> symmetrical. They either both look at one link only, or both go down to
>> the root port. Though it seems _capable() is link-local, and
>> _available() is down to root port.
>>
> 
> As you know, link speed is a qualification of two devices speed capability.
> Both speed and width parameters get negotiated by two devices during TS1 and TS2
> ordered set exchange. 
> 
> You need to see what your link partner can support in available function() vs.
> what this device can do in bandwidth() function.

I see. I'm not sure I can use pcie_print_link_status() without some
major refactoring. I need to look at capability of device and it
downstream port. There's no point complaining that an x16 device is
running at x4 when the port is only x4 capable.

Let me think some more on this.

Alex